90’s Kid Active-HDL Celebrates Sweet 16

Serving FPGA Designers as the tool of choice since, like, forever

Satyam Jani, Product Manager Software Division
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As the proud Product Manager of Aldec’s  FPGA Design Simulation solution,  I am excited (like it was my first Cranberries concert) to announce that Active-HDL™ is celebrating 16 years since its initial release in 1997. Active-HDL has not merely stood the test of time, it has dominated the FPGA market like a Hulk Hogan smackdown with powerful simulation performance and debugging tools.

The key to Active-HDL’s long-term success lies in Aldec’s customer-centric philosophy. Simply put, we really do listen closely to our users and invest heavily in our tools. For this reason, continued simulation performance optimizations from release to release enable users to benefit from Active-HDL’s faster simulation even as the size of FPGA designs continues to grow.

Active-HDL has even recently won the Top FPGA Design, Verification and Simulation Platform for the fourth consecutive year by Chinese Electronics News (CEN). Here’s an excerpt from today’s press release:

Active-HDL, Aldec’s all-in-one tightly integrated solution offering design creation, documentation, code coverage and simulation, was awarded the 2013 Excellence Award - FPGA Tools for the fourth consecutive year by Chinese Electronics News (CEN).  This prestigious award, recognizing top contributors in the semiconductor industry, was presented at China’s fifth annual FPGA Industry Development Forum.

“Active-HDL has evolved tremendously since its initial launch in 1997 and continues to be the tool of choice for FPGA designers,” said Satyam Jani, Aldec Software Division Product Manager, “Aldec’s receipt of this prestigious award demonstrates our commitment to investing in our products to continually meet the growing needs of the FPGA design community.”

You can view the rest of this press release in the Aldec Newsroom.

For more on Active-HDL including resources and free evaluation download, visit www.aldec.com/products/active-hdl or check out these resources:

White Paper: Corporate Standardization of FPGA Design Flow

Recorded Webinar (Part 1 of 3): Fast Track to Active-HDL


Satyam manages Aldec’s leading FPGA design entry and simulation tool – Active-HDL. He received his B.S. in Electronics Engineering from Sardar Patel University, India in 2003 and M.S in Electrical Engineering from NJIT, New Jersey in 2005.  His practical engineering experience includes areas in Solid state electronics, Digital Designing and functional verification. He has worked in wide range of engineering positions that include FPGA Design Engineer, Applications Engineer and Product Manager.


Oh, I do remember those days when we were testing Active-HDL before its first release. To put those times in perspective:
- our computers were running Windows 95
- inside those computers, Pentium processors were the norm (Pentium II was just released, so only the lucky ones had them)
- our monitors were CRTs, not LCDs
- floppy disk drive was the norm, with occasional CD drive
- no standard USB ports (you could get USB card)
- Centronics and RS-232 ports were ubiquitous
It is amazing how much good work design engineers could do with Active-HDL (actually, it was Active-VHDL at that time) on those puny machines...
Jarek K. over 3 years
Customer-focused is right - Aldec really takes your work seriously. I had a massive, ancient project that had to be completely updated for a new FPGA architecture. It didn't import smoothly - Aldec recognized the problem, devoted engineers to fix it, sent us patches (which everyone benefits from), and sent Satyam out in person to make sure everything went well - which it did! Compare this to Xilinx, who has cancelled their Webcase support. Whatever FPGA I use in the future, I'll use it with Active-HDL - Aldec is making constant improvements to it, the support rocks, and I'm excited there's a new release coming! I hope one day I get to work with CyberWorkBench as well - Go Aldec!
Travis A. over 3 years
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