Aldec Design and Verification Blog Trending Articles Bridging Simulation and Hardware Advanced Static Linting for FPGA Performance Optimization Scalable Cloud-based CI/CD HDL Verification Environment Navigating VUnit: A Practical Guide to Modifying Testing Approaches Speeding Up Simulation with VUnit for Parallel Testing Introduction to VUnit FPGA Design Verification in a Nutshell All Categories Corporate DO-254 Compliance Embedded Solutions Emulation/Acceleration FPGA Design Functional Verification High Performance Computing Requirements Management SoC and ASIC Prototyping SoC Design and Validation Specialized Applications Bridging Simulation and Hardware Hardware-in-the-Loop in Action Whether developing FPGAs, ASICs, or AI-enabled embedded systems, verification remains one of the most challenging and time-consuming phases of the development process. Hardware-in-the-Loop (HIL) testing is transforming this process.... Tags:Aceleration,Embedded,FPGA,Hardware,HDL,Prototyping,Simulation,Xilinx,Design Like(0) Comments (0) Read more Advanced Static Linting for FPGA Performance Optimization How to Boost Design Speed and Efficiency Accelerate FPGA Design with Advanced Static Linting In modern high-speed FPGA design, raw performance isn’t enough. Engineers face increasing challenges in achieving higher clock frequencies, lower power consumption, and smaller silicon footprints... Tags:FPGA,Prototyping,FPGA Simulation,Design,Hardware,HDL,Linting,safety-critical,Simulation,STARC,Verification,Xilinx Like(0) Comments (0) Read more SynthHESer - Aldec’s New Synthesis Tool In the early days of digital design, all circuits were designed manually. You would draw K-map, optimize the logic and draw the schematics. If you remember, we all did many logic optimization exercises back in college.... Tags:Xilinx,Aceleration,Design,Embedded,Emulation,HDL,SystemVerilog,Verilog Like(2) Comments (2) Read more Linting RISC-V designs with ALINT-PRO As the open-source RISC-V instruction set architecture (ISA) continues to gain momentum, the growing number of RISC-V design solutions, and their flexibility, creates a problem when choosing the most reliable and robust solution from a number of contenders.... Tags:ASIC,FPGA,HDL,Verification,Verilog,Design,Digital,IP,Linting,SoC,SystemVerilog Like(2) Comments (0) Read more Is your Verification plan pulling you in multiple directions? Try FSM Coverage A quick look into FSM Coverage The verification process is long and time consuming, especially when you are not sure what you are looking for. There are a lots of directions you can go looking for bugs but without a guide, without a plan you will most likely be going in circles.... Tags:Coverage,Debugging,Design,FPGA,SystemVerilog,Verilog,VHDL Like(1) Comments (8) Read more Verification Effectiveness with Riviera-PRO: SystemVerilog Randomized Layered Testbench Understanding SystemVerilog Layered Testbench In this blog, I will discuss randomized layered testbenches used in SystemVerilog. We need to understand why we need it, ... Tags:Riviera-PRO,ASIC,Assertions,Co-simulation,Coverage,Debugging,Design,Documentation,FPGA,HDL,IEEE,OS-VVM,Randomization,Simulation,standards,SystemVerilog,UVM,Verification,Verilog Like(4) Comments (0) Read more Do I really need a commercial simulator? A quick view of the benefits of a commercial simulator As an Applications Engineer I visit lots of potential customers, or talk to them at trade shows, who are doing FPGA designs but don’t own a commercial simulator. I ask them why that is. Most of the time it is budgetary restrictions. They don’t... Tags:Debugging,Design,Simulation,Verification Like(1) Comments (0) Read more ‘Don’t Be Afraid of UVM’ Webinar on YouTube Free webinar from the Aldec archives Just in time for Halloween, Aldec has released a popular past webinar Don’t be Afraid of UVM for Hardware Designers on YouTube. Designers are usually very busy doing their work and have little time left for experimentation... Tags:Design,Hardware,resources,SystemVerilog,UVM,Verification Like(2) Comments (0) Read more Helping FPGA Designers get started with UVM Guest Blog by Doulos CTO, John Aynsley UVM (the Universal Verification Methodology for SystemVerilog) represents best practice in constrained random functional verification, so it is something that every digital design and verification engineer should be aware of.... Tags:Design,FPGA,UVM Like(2) Comments (0) Read more Averting CDC Roadblocks in FPGA Design Design Rule Checking Best Practices This being my first summer in Las Vegas, it is the first time I’ve experienced the rainy, desert monsoon season and the powerful flash floods it can bring. Last week one of those monsoons, powered by the remnants of Hurricane Norbert,... Tags:Design,FPGA,Linting,Simulation Like(2) Comments (0) Read more
