Averting CDC Roadblocks in FPGA Design

Design Rule Checking Best Practices

Ajay Pradhan, Product Manager Software Division
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This being my first summer in Las Vegas, it is the first time I’ve experienced the rainy, desert monsoon season and the powerful flash floods it can bring. Last week one of those monsoons, powered by the remnants of Hurricane Norbert, produced floodwaters so strong they completely washed out a section of the I-15 Interstate north of town. With no road for several days, those traveling to and from Utah were forced to take a long detour, winding through nearby towns and wasting precious travel time.

An effective CDC solution for design rule checking can work much the same way, like a straight, clearly marked highway that quickly delivers you directly to your destination. Without such a solution, detouring past the many CDC issues that are becoming more pervasive in FPGA design can quickly become a long, winding road – and an inefficient use of time and resources.  I covered some of these CDC nightmares in a previous article, and in this post I’ll share some best practices to help avoid these roadblocks. I’ll also demonstrate how new CDC rule plugins (to be added later this year to ALINT™) can help in the mitigation of such issues.


Design Constraints

Aldec CDC Flow

  Fig 1. Aldec CDC Flow

A proper design rule check CDC flow begins with the creation of automatic design constraints. Constraining the design precisely is a must before running CDC checks to avoid misleading and incorrect error/warning messages.


ALINT with CDC rule plugins helps by generating the initial constraint automatically, which can be manually modified to add missing constraints. Constraint linting is performed by the tool to verify that the constraints match with the design structure and that all the required constraints has been specified.


ALINT with CDC rule plugins will also perform linting on the RTL based on CDC rules, flagging issues found in the design and complementing  traditional linting based on industry standards such as STARC, RMM, DO-254. Effectively, one will have the ability to perform linting based on the mentioned standard rules, while ensuring conformance of the same RTL for being CDC complaint. 


Static Verification

ALINT with CDC rule plugins offers structural analysis to find the asynchronous crossings that are missing synchronizers, or synchronized crossings which are incorrect due to a combinational logic, convergence and divergence issues. The tool can identify the various synchronizers like NDFF, Mux, Pulse, FSM, FIFO, RAM, Gray encoding and analyze the correctness of synchronizer.

Any CDC related rules violated are linked actively to the line of the code and the schematic representation of the same violating code. Some of these rules are described below:


1. Missing Synchronizer for cross over path

2. No combinational logic between asynchronous clock domains

3. No combinational logic between the first-stage FF and the next synchronizing FF

4. Avoid feedback loops at the first-stage FF after transfers between asynchronous clock domains

5. Convergence in CDC path detected

6. Divergence in CDC path detected

7. Divergence of meta-stable signal detected

8. Improper reset synchronization scheme

9. Inverted Clock not allowed for the first flip flop of CDC synchronizer

10. Gated clock is not allowed for the first flip flop of FF synchronizer


Dynamic Verification

Dynamic verification can be done with Aldec's Riviera-PRO™ simulator in conjunction with ALINT (Fig 2).


Simulator Integration

Fig 2. Simulator Integration


For metastability insertion, a random delay is inserted in the CDC Synchronizer, and simulation verifies that the CDC signal is captured across the domain by synchronizers using different delays (Fig 3).


Metastability insertion

Fig 3. Metastability insertion


ALINT also generates assertion for verifying the data stability during transfer. A sample for 2 DFF synchronizer is shown (Fig 4).


Assertions Sample Code

Fig 4. Assertions: Sample Code



ALINT with CDC rule sets in your FPGA design flow will pre-empt the chances of design failure during board debug and having to spend substantial time chasing the reason for the intermittent failures. 


If you’d like to learn more, and preview a demo of the new CDC features for ALINT, I invite you to view this recorded webinar, Static Design Rule Checks in FPGA Design.


For more on ALINT, visit www.aldec.com/products/alint or contact sales@aldec.com.

Ajay is a Product Manager at Aldec  for  DRC and CDC solutions. He received his BS  in Electrical Engineering from the National Institute of Technology, Jaipur, India and has 18 years of experience in the ASIC/FPGA and EDA industry. Ajay has worked for various companies in San Jose such as Xilinx, Mentor Graphics, Actel,  Microsemi  and Real Intent, and is experienced in roles such as as Design Engineer, Senior VLSI Engineer, Field and Corporate Application Engineering, Design Solutions, as well as building a Corporate Application Engineering Team from the bottom up as Manager of CAE at MicroSemi.


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