Partners

Aldec Design and Verification Blog

Trending Articles
The hardest part of DO-254 is…
Insight from Aldec’s 3-Day DO-254 Practitioner’s Course

The hardest part of DO-254 is not the requirements. It’s not the design. It’s not the verification.   We just wrapped up this year’s 3-day DO-254 Practitioner’s Course, and each year I learn something new. In this year’s training we had attendees...

Like(1) Comments (0) Read more
A Comprehensive RTL Verification Solution for VHDL
ALINT-PRO™ Design Rule Checking Solution

On Thursday, November 19, I’ll be hosting a webinar to demonstrate Aldec’s RTL Verification Solution for VHDL, ALINT-PRO™ Design Rule Checking Solution.   ALINT-PRO is Aldec’s design verification solution for RTL code...

Like(1) Comments (0) Read more
The Problem with CDCs
And how it affects your DO-254 project

Part of the Planning Process in DO-254 is knowing the appropriate FPGA tools and capabilities that you need and intend to use for your FPGA design. Particularly if your FPGA device...

Like(1) Comments (0) Read more
Developing high-reliability FPGAs for DO-254
Can you bet your life on your designs?

You have been developing FPGAs for a long time, and you know your designs from top to bottom. You know every interface protocol, configuration and optimization....

Like(2) Comments (0) Read more
It’s Here! ALINT-PRO-CDC™ for CDC Verification
Aldec’s new solution for complex multi-clock designs

I am happy to announce, that today Aldec has released ALINT-PRO-CDC™ 2015.01. This solution enables verification of clock domain crossings and handling of metastability issues in complex, modern multi-clock designs....

Like(1) Comments (0) Read more
Webinars, YouTube, Articles... What’s your preference?
Useful resources to help you get ahead

“USEFUL” is a word you’ll hear a lot over here at Aldec. It’s the number one way we rank our success when developing a new product or feature. “How USEFUL is it?” is the most common phrase we challenge one another...

Like(1) Comments (0) Read more
Spec-TRACER now directly integrated with IBM DOORS
You asked. We implemented.

In response to user feedback, Aldec has developed a direct integration between IBM® Rational ® DOORS ® and our requirements management tool, Spec-TRACER™, to enable users to extend the traceability data...

Like(0) Comments (0) Read more
Stress-Relief for Requirements-Based Verification
Verification of Safety-Critical FPGAs under Strict DO-254 Guidance

If they’re being honest, anyone who has verified an FPGA under strict DO-254 guidance will tell you that it is stressful. Show me an engineer on their first DO-254 project – and I’ll show you someone pulling out their hair...

Like(1) Comments (0) Read more
The 80s music at DAC was my idea. You're welcome.
DAC Chats to be presented live online

If you attended the Monday Night Reception at DAC 2014, you were greeted with a blast of 80s pop music. If you then said to yourself, “I’d like to meet the genius behind that idea” - that would be me. A few weeks before DAC...

Like(2) Comments (0) Read more
Does DO-254/CTS™ Support FPGAs with Serial High-speed I/Os?
A trending question from the DO-254 community

As a DO-254 evangelist, I travel quite a bit attending conferences and meeting customers all over the world. One question I occasionally get from engineers is whether Aldec’s mil/aero verification solution, DO-254/CTS™,...

Like(2) Comments (0) Read more
Ask Us a Question
x
Ask Us a Question
x
Captcha ImageReload Captcha
Incorrect data entered.
Thank you! Your question has been submitted. Please allow 1-3 business days for someone to respond to your question.
Internal error occurred. Your question was not submitted. Please contact us using Feedback form.
We use cookies to ensure we give you the best user experience and to provide you with content we believe will be of relevance to you. If you continue to use our site, you consent to our use of cookies. A detailed overview on the use of cookies and other website information is located in our Privacy Policy.