Aldec Design and Verification Blog Trending Articles Bridging Simulation and Hardware Advanced Static Linting for FPGA Performance Optimization Scalable Cloud-based CI/CD HDL Verification Environment Navigating VUnit: A Practical Guide to Modifying Testing Approaches Speeding Up Simulation with VUnit for Parallel Testing Introduction to VUnit FPGA Design Verification in a Nutshell All Categories Corporate DO-254 Compliance Embedded Solutions Emulation/Acceleration FPGA Design Functional Verification High Performance Computing Requirements Management SoC and ASIC Prototyping SoC Design and Validation Specialized Applications SynthHESer - Aldec’s New Synthesis Tool In the early days of digital design, all circuits were designed manually. You would draw K-map, optimize the logic and draw the schematics. If you remember, we all did many logic optimization exercises back in college.... Tags:Xilinx,Aceleration,Design,Embedded,Emulation,HDL,SystemVerilog,Verilog Like(2) Comments (2) Read more The Power of PCIe in Performance-based FPGA World Understanding High speed serial data transfer In today's world, when the entire computing industry is talking about high-performance and high-speed applications using FPGAs, just what are the factors that can assure such performance and speed?... Tags:Aceleration,ASIC,Co-simulation,Documentation,Embedded,Emulation,FPGA,FPGA Simulation,Hardware,HDL,IP,Prototyping,Simulation,SoC,Validation,Verification,Xilinx Like(3) Comments (0) Read more The Race to Zero Latency for High Frequency Trading The High-Frequency Trading (HFT) industry has received a lot of attention during the last few years. HFT is all about speed and minimizing latency: the faster you can run trading strategies and algorithms for analyzing minute price changes... Tags:Aceleration,Coverage,Verification,Verilog,VHDL Like(2) Comments (0) Read more Accelerating Simulation of Vivado Designs with HES Improve verification speedup with Aldec’s HES-DVM FPGA Design Verification Challenge The FPGA design and verification “ecosystem” changes rapidly to keep pace with the fast growing size of FPGA devices. The largest Xilinx Virtex UltraSCALE chips provide 4.4 Million logic cells... Tags:Aceleration,Co-simulation,FPGA,Simulation,Verification,Xilinx Like(1) Comments (0) Read more Scaling the “Internet of Things” With Aldec HES-DVM™ Happy New Year! January brought an unseasonably warm wave of weather to Las Vegas as International CES converged on the city this month. The size and scope of this worldwide consumer electronics tradeshow... Tags:Aceleration,Emulation,SoC,ASIC Like(2) Comments (0) Read more How HES™ Technology Solved Problems for These Users Verification and validation environment for SoC/ASIC designs Recognizing a problem that engineers are facing and developing a solution has been Aldec’s rather straight-forward mantra for going on thirty years now. Aldec launched its Hardware Emulation Solutions (HES) product in 2003,... Tags:Aceleration,Debugging,Embedded,Emulation,UVM,Verification Like(1) Comments (0) Read more HES-DVM™ 2013.11 Delivers Increased Speed and Debugging Introducing Turbo Mode and HesDebugApi Aldec recently released HES-DVM 2013.11 which introduces an array of customer-requested new features and improved debugging capabilities, speed, and co-emulation infrastructure.... Tags:Aceleration,Co-simulation,Emulation,SoC Like(0) Comments (0) Read more Leverage Hardware Acceleration for Faster Simulation Breaking the Bottleneck of RTL Simulation Utilizing hardware acceleration in a System-on-Chip verification cycle can speed-up HDL simulation runs from 10-100x, while providing the robust debugging available from an RTL simulator.... Tags:Aceleration,FPGA,Hardware Emulation,HDL Like(3) Comments (0) Read more Aldec and Xilinx, Partnered for Success HW/SW Emulation and Functional Verification of Xilinx FPGAs As an Aldec Hardware Product Manager, I make the quick flight from our home base in Las Vegas to San Jose pretty regularly. This week, I’ll be joining Aldec Software Product Manager, Dmitry Melnik, as we head out to attend... Tags:Aceleration,FPGA,SoC,Xilinx,Verification,Hardware Like(1) Comments (0) Read more Time-Saving, Hardware-assisted Verification For ASIC/SoC Designs Identifying effective processes for functional verification of ASIC and SoC designs is of increased significance for engineers due to growing design complexity and integration of embedded components such as CPUs, GPUs, and software device drivers. Overall test time for these systems can include millions... Tags:HES,Emulation,Aceleration,ASIC,SoC,Design,Validation,Verification,Prototyping,Debugging Like(1) Comments (0) Read more
