How HES™ Technology Solved Problems for These Users

Verification and validation environment for SoC/ASIC designs

Krzysztof Szczur, Hardware Verification Products Manager
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Recognizing a problem that engineers are facing and developing a solution has been Aldec’s rather straight-forward mantra for going on thirty years now. Aldec launched its Hardware Emulation Solutions (HES) product in 2003, integrating RTL simulation with hardware emulation, and offering hardware and software design teams the ability to work concurrently. Today HES™ is a fully automated and scriptable HybridVerification and Validation environment for SoC and ASIC designs capable of bit-level simulation acceleration, SCE-MI 2.1 transaction emulation, hardware prototyping, and virtual modeling. 


Take a look at some of the problems that HES Technology has been able to solve:



Use Case #1 - A Fabless Semiconductor Company

In this case, the user had many requirements including the verification of a 20 million gate design in bit level acceleration and SCE-MI transaction level emulation, and also required extensive debugging functions. The verification process was performed using HES technology (DVM, transactors and HES boards) in acceleration and SCE-MI emulation with all required debugging features, memory support and Virtual Platform integration.  [More Use Case Details]



Use Case #2 - An Electronics Firm R&D Division

This user needed a high-speed, hardware verification solution based on Virtex-7, a solution for RTL simulations that were running too long and   FPGA boards for prototyping (with ability to reuse hardware for other verification modes like  acceleration and emulation). They began with HES acceleration, Aldec also presented SCE-MI emulation mode and provided AXI transactors for emulation with added custom transactors.  The result was over 150x speedup over RTL simulations. [More Use Case Details]


These use cases illustrate Aldec’s commitment to work closely with engineers to understand their problems and deliver solutions. Among these problems is rising software costs that are now dominating SoC design. Aldec has partnered with FirstEDA to address these issues in a webinar.

This webinar illustrates why FPGAs are chosen as the verification platform for software integration and discuss the challenges of using FPGAs for verification and introduce the use of hybrid virtual prototypes. A comparison is also made between traditional FPGA ASIC prototypes and an FPGA-based emulation system.


Recorded Webinar:

Accelerating The Verification Of Hardware Dependent Software

Presenter: Alex Grove, FirstEDA Applications Specialist

For more on HES, visit or contact


Krzysztof joined Aldec in 2001 and was a key member of the team that developed HES-DVM™, Aldec's FPGA-based simulation acceleration and emulation technology. He has worked in the fields of HDL IP-core verification, testbench automation and design verification for DO-254 compliance gaining practical experience and deep understanding of design verification methodologies, emulation and physical prototyping. As Hardware Verification Products Manager, Krzysztof cooperates with key customers and Aldec's R&D to overcome complex design verification challenges using Aldec hardware tools and solutions. Krzysztof graduated as M.Eng. in Electronic Engineering (EE) at the AGH University of Science and Technology in Krakow, Poland


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