Aldec Design and Verification Blog Trending Articles Code Coverage in HDL Editor? Now That’s a Nice Feature. Zynq-based Embedded Development Kit for University Programs Understanding the inner workings of UVM Synthesis of Energy-Efficient FSMs Implemented in PLD Circuits Don’t be a Slave to the Documentation Demystifying AXI Interconnection for Zynq SoC FPGA Accelerating Simulation of Vivado Designs with HES All Categories Corporate DO-254 Compliance Embedded Emulation/Acceleration FPGA Design Functional Verification High Performance Computing Req Life Cycle Mgmt SoC and ASIC Prototyping SoC Design and Validation Specialized Applications TySOM Code Coverage in HDL Editor? Now That’s a Nice Feature. For a long time I have been a fan of code coverage tools that are embedded into the simulators themselves, and which give you the ability to switch easily between the code and the coverage results. It is particularly helpful to have a way... Tags:Verification,Verilog,VHDL,Coverage Like(0) Comments (0) Read more Zynq-based Embedded Development Kit for University Programs Cost-effective solution for HW/SW development projects Creativity and innovation, which lead the society to success, rest on the foundational institutions such as schools and universities. They provide fertile soil to seed, grow and flourish enterprises.... Tags:Co-simulation,Embedded,FPGA,HDL,Prototyping,Simulation,SoC,university,Xilinx,Design,Digital Like(0) Comments (0) Read more Understanding the inner workings of UVM UVM Basics Part 1 of 3 We have all been witnesses to the rapid improvements of the iPhone processor chip every year. With the iPhone 8 featuring the newest A11 Bionic at 10 nm FinFET with 4.3 billion transistors, I can’t personally fathom the amount... Tags:ASIC,Co-simulation,Coverage,Debugging,Documentation,FPGA,OS-VVM,UVM,Verification Like(1) Comments (0) Read more Synthesis of Energy-Efficient FSMs Implemented in PLD Circuits Finite State Machines in low-power world Well, summer has been and gone; and for most of us it was a time to relax and reflect on our working practices. What can we do to achieve better results? And what can we do to break out of the routine of working on so many revisions?... Tags:FPGA,university,Verification Like(1) Comments (0) Read more Don’t be a Slave to the Documentation Are you a requirements engineer but your main goal is to provide well organized documentation? Do you have a great knowledge about the industry, business analysis and systems but you are struggling with the shape and look of your documentation?... Tags:ASIC,Documentation,FPGA,Project management Like(0) Comments (0) Read more Demystifying AXI Interconnection for Zynq SoC FPGA Analyzing the interface between the processing unit and programmable logic in the Zynq architecture Imagine traveling back in the time to the early human ages. It’s going to be both scary and interesting when you meet a person who probably cannot speak or if they do you won’t be able to understand them.... Tags:ARM,FPGA,SoC,Xilinx,Zynq,TySOM,AXI Interconnection Like(0) Comments (0) Read more Introduction to Zynq™ Architecture A brief examination of the Zynq processing system and its programmable logic The History of System-on-Chip (SoC) Do we prefer to have a small electronic device or a larger one? The answer will often be “the smaller one”. However, before the commercialization of small radios, many people were interested in having... Tags:ARM,Embedded,FPGA,Hardware Like(0) Comments (0) Read more Accelerating Simulation of Vivado Designs with HES Improve verification speedup with Aldec’s HES-DVM FPGA Design Verification Challenge The FPGA design and verification “ecosystem” changes rapidly to keep pace with the fast growing size of FPGA devices. The largest Xilinx Virtex UltraSCALE chips provide 4.4 Million logic cells... Tags:Aceleration,Co-simulation,FPGA,Simulation,Verification,Xilinx Like(0) Comments (0) Read more Traceability Matrices: Headache or Real Value Traceability is becoming increasingly important in most engineering projects, if only on the grounds of ‘good practice’, and it is specifically required for projects that have to meet safety standards such as DO-254 and ISO 26262.... Tags:FPGA Like(2) Comments (0) Read more VHDL-2017: Some of My Favorite Things For the past several years I have had the privilege to chair the IEEE 1076 VHDL working group. In March we handed off the revisions to the VHDL LRM to our technical editor to finalize the document for balloting. As we are waiting for the standards process to finish up, I thought I would share my favorite new additions. Let me start with an executive summary: ... Tags:HDL,IEEE,Simulation,Verification,VHDL Like(3) Comments (0) Read more
