Aldec Design and Verification Blog Trending Articles No Risk No Fun What is Bird’s Eye View ADAS Application and How to Develop This Using Zynq® UltraScale+™ MPSoC FPGA? HW/SW Co-Simulation for SoC FPGA designs The Power of PCIe in Performance-based FPGA World Problems Accessing Registers? – See how UVM RAL can help The Race to Zero Latency for High Frequency Trading FPGA vs GPU for Machine Learning Applications: Which one is better? All Categories Corporate DO-254 Compliance Embedded Solutions Emulation/Acceleration FPGA Design Functional Verification High Performance Computing Requirements Management SoC and ASIC Prototyping SoC Design and Validation Specialized Applications No Risk No Fun At the end of February, I attended the Aero Show in India - and what a show it was. So many exhibitors from around the world, including all main players from the commercial and military sides of the aerospace industry. Visitors could see everything required to build a modern aircraft; from small components like specialized ICs, cables and connectors up to big parts, such as the jet engines, landing gear assemblies and structural components.... Tags:FPGA,safety-critical,Verification,DO-254 Like(3) Comments (0) Read more What is Bird’s Eye View ADAS Application and How to Develop This Using Zynq® UltraScale+™ MPSoC FPGA? Bird’s eye view definition, HW/SW setup and implementation algorithms Will the world be a better place in which to live by having autonomous cars driving around us? Or would it be unsafe and scary? Maybe someone was asking such a question even when the first steam-powered automobile capable... Tags:Aceleration,ARM,Embedded,FPGA,Hardware,HDL,Prototyping,Validation,Verification,Verilog,Design,Digital,SoC,Xilinx,Zynq Like(0) Comments (0) Read more HW/SW Co-Simulation for SoC FPGA designs Aldec’s Co-Simulation Solution using QEMU and Riviera-PRO Heterogeneous System on Chip (SoC) devices like the Xilinx Zynq 7000 and Zynq UltraScale+ MPSoC combine a high-performance processing system (PS) with state-of-the-art programmable logic (PL).... Tags:Co-simulation,Embedded,FPGA,Hardware,HDL,Simulation,SoC,Validation,Verification,Verilog,VHDL,Xilinx Like(1) Comments (0) Read more The Power of PCIe in Performance-based FPGA World Understanding High speed serial data transfer In today's world, when the entire computing industry is talking about high-performance and high-speed applications using FPGAs, just what are the factors that can assure such performance and speed?... Tags:Aceleration,ASIC,Co-simulation,Documentation,Embedded,Emulation,FPGA,FPGA Simulation,Hardware,HDL,IP,Prototyping,Simulation,SoC,Validation,Verification,Xilinx Like(2) Comments (0) Read more Problems Accessing Registers? – See how UVM RAL can help As a digital design or verification engineer you know that certain features or configurations of the device can be achieved by programming some registers to set values.For example, a 32-bit register can have several fields within it... Tags:ASIC,Debugging,FPGA,Simulation,SystemVerilog,UVM,Verification Like(1) Comments (0) Read more The Race to Zero Latency for High Frequency Trading The High-Frequency Trading (HFT) industry has received a lot of attention during the last few years. HFT is all about speed and minimizing latency: the faster you can run trading strategies and algorithms for analyzing minute price changes... Tags:Aceleration,Coverage,Verification,Verilog,VHDL Like(1) Comments (0) Read more FPGA vs GPU for Machine Learning Applications: Which one is better? Can FPGAs beat GPUs? FPGAs or GPUs, that is the question. Since the popularity of using machine learning algorithms to extract and process the information from raw data, it has been a race between FPGA and GPU vendors to offer... Tags:Aceleration,Embedded,FPGA,Hardware,HDL,Validation,Verilog,VHDL,Xilinx Like(1) Comments (0) Read more Verification Effectiveness with Riviera-PRO: SystemVerilog Randomized Layered Testbench Understanding SystemVerilog Layered Testbench In this blog, I will discuss randomized layered testbenches used in SystemVerilog. We need to understand why we need it,... Tags:Riviera-PRO,ASIC,Assertions,Co-simulation,Coverage,Debugging,Design,Documentation,FPGA,HDL,IEEE,OS-VVM,Randomization,Simulation,standards,SystemVerilog,UVM,Verification,Verilog Like(3) Comments (0) Read more Do I really need a commercial simulator? A quick view of the benefits of a commercial simulator As an Applications Engineer I visit lots of potential customers, or talk to them at trade shows, who are doing FPGA designs but don’t own a commercial simulator. I ask them why that is. Most of the time it is budgetary restrictions. They don’t... Tags:Debugging,Design,Simulation,Verification Like(0) Comments (0) Read more Understanding the inner workings of UVM - Part 3 UVM Basics Part 3 of 3 In this blog, I am going to discuss different phases that UVM follows. The reason why UVM came up with such phases is because synchronization among all design-testbench was necessary. Using Verilog and VHDL,... Tags:ASIC,Co-simulation,Coverage,Debugging,Documentation,FPGA,OS-VVM,UVM,Verification Like(1) Comments (3) Read more
