Aldec Design and Verification Blog Trending Articles Aldec Engineers: Taking Action and Giving Back as a Team Introduction to AXI Protocol It’s Time to Get Your University in Sync with Zynq The UVM Configuration Database To Emulate or Prototype? The hardest part of DO-254 is… Aldec Verification Tools Implement the ASIC Verification Flow All Categories DO-254 Compliance Embedded Emulation/Acceleration FPGA Design Functional Verification Req Life Cycle Mgmt SoC and ASIC Prototyping SoC Design and Validation Specialized Applications Aldec Engineers: Taking Action and Giving Back as a Team The Annual Katowice Business Run For engineers, the importance of keeping active cannot be understated. When thousands of hours are spent seated in front of monitors, healthy activities such as running are more than fun... they are necessary. At Aldec, our team... Tags:Training Like(1) Comments (0) Read more Introduction to AXI Protocol Understanding the AXI interface When part of a team, your group can become more capable than a single individual, but only if your team can work together and communicate effectively. Having members of a group talk over each other leads to nothing but a cacophony, and nothing gets done. For ... Tags:ARM,Embedded,Xilinx,Zynq Like(0) Comments (0) Read more It’s Time to Get Your University in Sync with Zynq Insight From a College Student It’s time for Universities to say goodbye to their outdated FPGA boards and introduce the Xilinx® Zynq™ chip. The Zynq chip is a device which combines an FPGA fabric with a processing unit. The Zynq chip is very similar to other FPGA devices, but ... Tags:FPGA,Hardware,Embedded,SoC,VHDL,Xilinx,Zynq Like(1) Comments (0) Read more The UVM Configuration Database Keeping a neat repository for flexible testbench structure When I want to wear a certain clothing item, I take out it of the closet. When I go shopping, I add those clothes it to my closet and there are now new items for me to pick out in the future.... Tags:Simulation,UVM,Verification Like(0) Comments (0) Read more To Emulate or Prototype? Is it even a question? Recently I read a Semiwiki article, Army of Engineers on Site Only Masks Weakness, in which author Jean-Marie Brunet of Mentor Graphics wrote that FPGA Prototyping requires an army of tech support engineers on-site to mask... Tags:Emulation,FPGA,Prototyping,Xilinx Like(0) Comments (0) Read more The hardest part of DO-254 is… Insight from Aldec’s 3-Day DO-254 Practitioner’s Course The hardest part of DO-254 is not the requirements. It’s not the design. It’s not the verification. We just wrapped up this year’s 3-day DO-254 Practitioner’s Course, and each year I learn something new. In this year’s training we had attendees... Tags:FPGA,safety-critical,Verification Like(0) Comments (0) Read more Aldec Verification Tools Implement the ASIC Verification Flow Insights from Dr. Stanley Hyduke, Aldec Founder and CEO Aldec has, over the last 30 years, established itself as the preferred provider of high-performance, cost-effective verification tools for use in proving out complex FPGA designs. As the logic capacity and capability... Tags:Aceleration,ASIC,Emulation,Linting,Prototyping,Simulation,Verification Like(0) Comments (0) Read more Vegetarian Dining in Austin - DAC 2016 Helpful Tips From a Local I moved to Austin a little over a year ago, and have quickly learned that this city is a progressive blue island in a sea of red. That's the conventional wisdom, and most of the time it holds up.... Tags:ASIC,Emulation,Verification Like(0) Comments (0) Read more Acceleration-Ready UVM Guest Blog by Doulos CTO, John Aynsley We hear that emulation is one of the fastest-growing segments in EDA right now, yet simulation still continues to be the main workhorse for functional verification, and SystemVerilog and UVM are everywhere you look.... Tags:Aceleration,Emulation,Hardware,SystemVerilog,UVM,Verification Like(0) Comments (0) Read more UVM Register Layer: The Structure Creating an anatomically correct model for poking and prodding. I don’t know about you, but I am looking forward to the day where we won’t even have to go to the doctor’s office for an exam. Instead, we will all have scanners in our homes that will transmit full digital models to our doctors... Tags:Simulation,UVM,Verification,Verilog Like(1) Comments (0) Read more
