Aldec Design and Verification Blog

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Do I really need a commercial simulator?
A quick view of the benefits of a commercial simulator

As an Applications Engineer I visit lots of potential customers, or talk to them at trade shows, who are doing FPGA designs but don’t own a commercial simulator. I ask them why that is. Most of the time it is budgetary restrictions. They don’t...

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Understanding the inner workings of UVM - Part 3
UVM Basics Part 3 of 3

In this blog, I am going to discuss different phases that UVM follows.   The reason why UVM came up with such phases is because synchronization among all design-testbench was necessary. Using Verilog and VHDL,...

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SystemVerilog Functional Coverage in a Nutshell
Use native SystemVerilog constructs as metrics for verification closure in Riviera-PRO

Let’s say you have a block you need to verify. How do you know that the stimulus you are about to use is exhaustive enough and that you have covered the necessary scenarios/situations to prove it is working correctly?...

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Trace Your Assertions

When I enter the word “assertions” into a search engine I get lots of results, including articles, books, courses, and tools. Nothing unusual there, as assertions have been present in the EDA industry for many years. They considerably increase...

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Unit Linting: An easy way to prevent code review issues

Code reviews, aren’t they a pain? Every time you have to go through one, you find yourself thinking: “Why oh why I didn’t fix this thing in the beginning? It’ just a small formatting issue, but there are 100 files that have the same issue. I forgot to add comments to the state machines and I did not label my processes”. These very small issues may, in no way, affect the functionality of your design, but they are, say, required by your design guidelines. Don’t you wish you had done this right from the beginning?   Verification takes up to 70% of your design/verification process. And out of that 70%, how much do you think is just going back and fixing simple things that don’t really matter to design, but are required by company policy or design requirements? Wouldn’t it be nice to have a mechanism that will help with this? A quick way to run some checks while you are creating these files, so it will tell you what you are missing?   The good news: there is such a thing and it’s called Unit Linting, present in the recent 10.5 version release of Active-HDL 10.5; specifically in the tool’s HDL editor. If you own the Expert Edition license, you already have the ALINT-PRO license with the ALDEC basic ruleset included in that license. And if you didn’t know that, you are missing out on a great tool that will help you with linting checks on your design.     Before, you had to open your design in ALINT and run the linting process as a separate flow from your Active-HDL Workspace. Now, in Active-HDL 10.5, some linting features are included as part of the Active-HDL design, with the main one being the unit linting feature.   In the Active-HDL toolbar there is now a new button that will run unit linting on the open file and display the violations (right there, in Active-HDL console). Talk about convenience. You don’t have to launch another tool and/or load a new workspace, as you had to in the past. All you need to do is press one button in Active-HDL to expose all the unit lint violations. This integration lets you work on your design and simulations plus run linting from the same interface. Also, you have the added benefit of cross-probing directly to the line of the code that has caused the violation from the messages displayed in the console.   These unit level checks are only module level; i.e. it gives you the violations associated with that file alone. But when you are done with all your files, you can launch ALINT-PRO from within Active-HDL, just with a few clicks, and the tool will create a new workspace and design in ALINT-PRO and will add all the files needed, so you can run a full design level linting.     If you are a Riviera-PRO user don’t worry, we did not forget you. The next version of Riviera-PRO, the 2018.02, will have the same feature as listed above....

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How to develop an FPGA-based Embedded Vision application for ADAS, series of blogs – Part 1
FPGA “The winner for the low-power and high-performance vision-based applications”

When should we use the term “Vision for Everything”, as vision-based applications are entering various industries? It’s been a few years since the emergence of...

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Understanding the inner workings of UVM - Part 2
UVM Basics Part 2 of 3

In this blog, my major focus is on explaining the concepts such as Sequence, Sequencer, Driver and showing how the communication takes place from sequence to sequencer and from sequencer to driver. In the previous blog, I included...

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How to Design the New Generation of Reprogrammable Router/Switch Using Zynq FPGA
A must for high-traffic network

A high-performance router is an absolute must if you want to run a high-traffic network in which different devices need to transfer and receive data as fast as possible. A router with a powerful processor and sufficient local memory...

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Partition your Design for FPGA Prototyping
Easily create partitions with HES-DVM

Modern ASIC and SoC designs have increased in complexity such that multiple FPGAs of the largest capacity are now required to prototype the entire functionality of the design. As design sizes increase, more and more...

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Plots: A New Way To Analyze Data

Data analysis is often a very time consuming process for a hardware design or verification engineer. We always end up using the waveform viewer which may not be very efficient in giving us a high-level overview of what we’re looking for. Data that is spread across...

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