Active-HDL Configurations

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Design Entry and Documentation
HDL, Text, Block Diagram and State Machine Editor
With Active-HDL, you can mix different types of descriptions. Your design can include textual HDL code as well as block diagrams and state diagrams. More   
yesyesyesyes
Language assistant with templates and auto-complete
The Language Assistant is a tool designed to help you develop HDL, Handel-C, or SystemC source code, and Aldec macro commands. More   
yesyesyesyes
Macro, Tcl/TK, Perl script support
Aldec simulators support several scripting methods varying in the level of abstraction and possible applications. More   
yesyesyesyes
Mouse Strokes
Perform common and repetitive task by simply moving the mouse. For example, you can zoom in and out by simply holding a right mouse button and moving your mouse up or down. More   
yesyesyesyes
Code2Graphics™ Converter
The Code2Graphics converter is a tool designed for automatic translation of text sources into Active-HDL block and state diagrams. More   
yes-yesyes
Legacy Schematic Design Import and Symbol Import/Export
Active-HDL provides utilities for importing legacy schematic based designs from Xilinx Foundation Series, ViewLogic ViewDraw series, or any schematic tools that can output an EDIF netlist. More   
yes-yesyes
Export to PDF/HTML/Bitmap Graphics
The ability to quickly document designed components is becoming critical with the increased complexity of designs, ubiquitous IP re-use, and design teams scattered across many floors, departments, or countries. More   
yes-yesyes
Advanced Export to PDF (Vector Graphics)
Individual designs as well as workspaces can be exported to PDF. The export process is controlled by a wizard with wide selection of export options allowing creation of hot-linked PDF documentation well suited to any needs. More   
Option-yesyes
Project Management
Design Flow Manager for All FPGA Vendors
The Design Flow Manager configures, constrains and executes simulation, synthesis and implementation tools for all devices from Altera®, Atmel®, Lattice®, Microsemi™ (Actel), Quicklogic®, Xilinx® and more in one integrated development environment. More   
yesyesyesyes
Revision Control Interface
Active-HDL provides a powerful feature that allows communication and collaboration with a number of leading Source Revision Control systems. More   
yesyesyesyes
Team-based Design Management
Complex FPGA projects are often managed between various teams and require collaboration between team members. Its crucial to have a powerful design management tool that allows teams to collaborate on projects rapidly. More   
yesyesyesyes
Workspace and Design Archiving
To prevent accidental design file deletions and to provide you with additional exchange and backup options, Active-HDL comes with an Archive Design feature that allows archiving the current design or entire workspace into a single ZIP file. More   
yesyesyesyes
Support for Multi-Design Workspace
Designers can open multiple Active-HDL designs simultaneously and integrate them into one super-project. More   
--yesyes
PCB Interface (Automated FPGA I/O synchronization)
Aldec and its Partners have worked together to create an integrated solution that offers PCB designers a smooth migration between PCB design capture and HDL based FPGA design management and simulation products. More   
--yesyes
Code Generation Tools
IP Core Component Generator
The IP CORE Generator is a tool built-into Active-HDL that comes with a rich set of parameterized modules. They are ready-to-use in any VHDL- or Verilog-based system. More   
yes-yesyes
VHPI/PLI/VPI, SystemC Transactor and New File Wizards
The Verilog PLI interface provides a standard mechanism to access and modify data in a simulated Verilog model. The PLI interface creates user-defined tasks and functions that interact with Active-HDL. More   
yes-yesyes
Testbench Generation from Waveforms
Powerful testbench generation automation features have been provided to speed functional verification. A testbench for any design unit can be generated from waveforms created in the waveform editor or during a simulation run. More   
--yesyes
Testbench Generation from State Diagram
An auxiliary verification tool built-in to Active-HDL that creates testbenches used to test the HDL code generated by the State Diagram Editor. More   
--yesyes
Supported Standards
VHDL IEEE 1076 (1987, 1993, 2002 and 2008)
ALDEC simulators provide full support of the IEEE 1076-1993 Standard, IEEE 1076™-2002 VHDL standard and majority of just published IEEE 1076™-2008 Standard. More   
yesyesyesyes
Verilog® HDL IEEE 1364 (1995, 2001 and 2005)
ALDEC simulators provide full support of the IEEE 1364-2005 Standard. To enable simulation of a large variety of Verilog designs, both legacy and new, ALDEC simulators can be set to work in Verilog ’95, 2001 and 2005 modes. More   
yesyesyesyes
SystemVerilog IEEE 1800-2009 (Design)
SystemVerilog is a set of extensions to the Verilog HDL that allow higher level of modeling and efficient verification of large digital systems. More   
yesyesyesyes
EDIF 2 0 0
Simulation of netlist in EDIF 2 0 0 format is supported by most Aldec Simulators. More   
--yesyes
SystemC™ 2.3 IEEE 1666™/TLM 2.0
SystemC is a C library that extends C to enable hardware modeling. Although strictly a C class library, SystemC is sometimes viewed as being a language in its own right More   
--Optionyes
Simulation/Verification
Simulation Performance
Active-HDL includes simulation optimization features for both VHDL and Verilog which accelerate the simulation and cut simulation time significantly. More   
-BenchmarkBenchmarkBenchmark
Single or Mixed Language Design Support
Most ALDEC simulator configurations support mixed (VHDL and Verilog) designs, but single language (VHDL-only or Verilog-only) configurations are also available. More   
-Mixed Onlyyesyes
Verilog Programming Language Interface (PLI/VPI)
The Verilog PLI (Programming Language Interface) and VPI (Verilog Procedural Interface) provide a standard mechanism to access and modify data in a simulated Verilog model. More   
yesyesyesyes
VHDL Programming Language Interface (VHPI)
The VHPI interface provides a standard means to access data in VHDL models elaborated in Active-HDL and Riviera-PRO. More   
--yesyes
Language Interface Wizard (PLI/VPI/VHPI/DPI)
Language Interface Wizard (PLI/VPI/VHPI/DPI) More   
--yesyes
SystemVerilog IEEE DPI w/Wizard
The DPI-C wizard allows you to enter the names of DPI-C tasks and functions, their arguments (name, type, mode, and, optionally, the default value and range). More   
--yesyes
Simulation Model Protection
Library protection offers four security levels when compiled models are distributed in the form of library files without releasing their source code. More   
-yesyesyes
Verilog® IEEE 1364™-2005 Encryption
Using standard design source encryption is a much easier form of managing IP creation and delivery than any kind of binary file encryption. Riviera-PRO supports standard methodology introduced in IEEE Std. 1364-2005. More   
-yesyesyes
VHDL IEEE 1076™-2008 Encryption
Using standard design source encryption is a much easier form of managing IP creation and delivery than any kind of binary file encryption. Riviera-PRO supports standard methodology introduced in IEEE Std. 1076-2008. More   
-yesyesyes
Value Change Dump (VCD and Extended VCD) Support
The VCD (Value Change Dump) file format is specified in the IEEE Std. 1364-1995 standard. The VCD file is an ASCII file containing header information, variable definitions, and variable value changes. More   
-yesyesyes
Batch Mode Simulation/Regression (VSimSA)
VSimSA is a standalone VHDL/Verilog simulation environment designed for batch processing. More   
--yesyes
Profiler (Performance Metrics)
The Profiler identifies design units or code sections that put the greatest strain on the simulator. This information is valuable for optimizing the simulation environment and improving performance. More   
--Optionyes
Pre-compiled FPGA Vendor Libraries
Pre-compiled libraries for various FPGA vendors (Microsemi™ (Actel), Altera®, Lattice®, Xilinx® and others) are provided with Active-HDL. More   
yesyesyesyes
Altera® Language-Neutral Libraries
This option enables Aldec customers with VHDL only license to simulate the most recent Altera Libraries and Megafunctions without purchasing a separate Verilog license (which is required as some of the design units, as well as Megafunctions generated by the MegaWizard™ in Quartus® 11.0, are written in Verilog/SystemVerilog). More   
-yesyesyes
Microsemi® Language-Neutral Libraries
This option enables Aldec customers with VHDL-only license to simulate the Microsemi IP without purchasing a separate Verilog license More   
-yesyesyes
Xilinx® SecureIP Support
Aldec simulators support the SecureIP methodology of IP delivery implemented in Xilinx tools. More   
-yesyesyes
SFM (Server Farm Manager)
Server Farm Manager is an advanced tool working on the local network that allows users to schedule tasks and then execute them automatically on the selected computers available on the network. More   
-OptionOptionOption
64-bit Simulation
The ability for the simulator to run at 64-bit bus throughput application speeds and utilize extended memory. More   
--Optionyes
Debug and Analysis
Hierarchy Viewer with Configurations Support
The Design Hierarchy Viewer is a tool that allows designers to display the project's structure without its elaboration. More   
yesyesyesyes
Interactive Code Execution Tracing
Stepping through source code is one of the most common debugging procedures. Stepping is executing code one line at a time More   
-yesyesyes
Advanced Breakpoint Management
Simulations can be stopped on a breakpoint. Aldec supports both breakpoints in the source code as well as signal breakpoints. More   
-yesyesyes
Signal Probes on Graphics/Animation of Graphics
Aldec simulators can maintain communication with graphical design sources during simulation and can push live values of ports and signals to the Block Diagram Editor, where they can be displayed in the shape of colorful probes. More   
-yesyesyes
Memory Viewer
The Memory Viewer is a debugging tool that has been designed to display memory objects defined in an active design. More   
-yesyesyes
FSM Debug
Active-HDL provides features that help users to debug their bubble diagrams, including object sorter, diagram report, trace over transition, current state highlight, etc. More   
-yesyesyes
Waveform Viewer
The Accelerated Waveform Viewer is a high performance tool for graphical presentation of simulation data stored in a binary simulation database (*.asdb). More   
-yesyesyes
Multiple Waveform Windows
In large designs where multiple signals must be observed during simulation, keeping them in one waveform window is inconvenient: since all signals cannot fit in one window, frequent scrolling is required to get to the desired waveform data. More   
-yesyesyes
Waveform Stimulator
When quick checking of some parts of a large design is required, creating a testbench is not economical: testbenches work best while testing complete designs during multiple runs of simulation. More   
-yesyesyes
Waveform Comparison and Editor
A fast Waveform Viewer is an indispensable analysis tool, but signal data must be modified from time to time. More   
--yesyes
Post Simulation Debug
Post Simulation Debug is an advanced feature that allows users to observe the simulation results after the simulation has been finished. More   
--yesyes
C++ Debugger
The C Code Debug option is a feature that allows designers to debug PLI, VHPI, SystemC, or C/C++ source code with the open-source gdb debugger. More   
--yesyes
Signal Agent (VHDL and Mixed Only)
The Signal Agent in VHDL allows monitoring and driving VHDL signals from any VHDL block. Signals do not have to be routed via the interface or declared in global packages. More   
--yesyes
X-Trace
X-Trace helps you quickly identify the cause of unexpected values by reporting information on changes from valid to unknown, uninitialized, or user-defined values in the simulated model. More   
--yesyes
Dataflow
The Dataflow window is a powerful tool that allows designers to explore the connectivity of an active design and analyze dataflow among instances, concurrent statements, signals, nets, and registers during simulation. More   
--yesyes
Extra Standalone Accelerated Waveform Viewer (ASDB)
The stand-alone Waveform Viewer can be used to: display simulation results created in previous simulation runs and display simulation results on the fly, while simulation is still in progress. More   
--OptionOption
Integration with Riviera-PRO and ALINT
Integration with Riviera-PRO and ALINT is one-click interface that allows users to invoke Riviera-PRO and ALINT from within Active-HDL. Using this integration, users can export their Active-HDL projects to Riviera-PRO and ALINT during different design stages, such as simulation and linting. More   
Option-Optionyes
Assertions Debugging
Design and verification engineers who implemented assertions and covers in their project can observe their behavior during regular simulation and debugging in multiple windows. More   
--Option1yes
Assertions and Coverage Tools
Code Coverage (Statement/Branch, Expression/Condition, Path), Toggle Coverage, Functional Coverage (OSVVM)
Code Coverage is a debugging tool that aids the verification process. Active-HDL allows verifying source code with the following Code Coverage tools: More   
--yesyes
PSL IEEE 1850, SystemVerilog IEEE 1800™, OpenVera Assertions and Functional Coverage (Assertion)
Specification of properties and their use in assertions and functional coverage is the essential element of designing modern systems and their verification algorithms. More   
--Optionyes
Design Rule Checking
ALINT with Basic Rule Library
Aldec® ALINT™ analyzes VHDL, Verilog and Mixed Language HDL code during compilation, prior to simulated or synthesized. More   
--Option2yes
STARC Verilog or VHDL Rule Library
STARC® based programmable design and coding guideline checker of complex system-on-chip designs. More   
--Option2Option2
DO-254 Verilog or VHDL Rule Library
ALINT supports new sets of rules that facilitate compliance with DO-254. More   
--Option2Option2
RMM (VHDL and Verilog)
Reuse Methodology Manual (RMM) design rule library is based on the industry-proven manual from Synopsys Inc. and Mentor Graphics Corp. which defines the methodology for effective design reuse and verification. More   
--Option2Option2
Co-Simulation Interfaces
MathWorks Simulink®
The Simulink Interface simplifies verification of hardware designs by providing robust visualization and analysis toolsets. More   
--yesyes
MathWorks MATLAB®
Aldec simulators integrate The MathWorks' intuitive MATLAB language and a technical computing environment. More   
--Optionyes
Licensing
Node Locked or Floating License
Node Locked License More   
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One Year Time Based License
One Year Time Based License (TBL) grants a designer a license to use the product for a period of one year. A 1 year support contract is included with the purchase of TBL license. More   
yesyesyesyes
Perpetual License
A perpetual license is a license with no expiration date. A 1 year support contract is included with the purchase of perpetual license. More   
yes-yesyes
Supported Platforms
Windows® 10/8.1/8/7/2012/2008/2003 - (32/64-Bit)
Builds are tested on all the latest platforms to ensure correct operation on users' workstations. More   
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Option1 - Requires PSL IEEE 1850, SystemVerilog IEEE 1800™ and OpenVera Assertions feature
Option2 - ALINT™ is a separate Aldec product, STARC, DO-254 and RMM packages are sold separately
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