Simulation Performance

Category : Simulation/Verification



  Small Density FPGAs Medium Density FPGAs Large Density FPGAs
VHDL Baseline 3x Faster than DES 1.5x Faster than PE
Verilog Baseline 3x Faster than DES 3x Faster than PE
Mixed Baseline 3x Faster than DES 2x Faster than PE

All results are based on running an average of 100 designs. All designs are FPGA designs and results could vary on your design

PC Resources: Windows 7 Professional, 64Bit, i5-2400, 3.10GHZ with 8GB RAM

Active-HDL includes simulation optimization features for both VHDL and Verilog which accelerate the simulation and cut simulation time significantly.
These optimizers are tuned at a different level in various configurations of Active-HDL. Active-HDL Designer Edition is tuned at a pre-defined baseline speed which is still faster than vendor provided simulators in most cases.
There are two types of simulation optimizers:

1.Verilog RTL & Gate Performance Optimization
2.VHDL RTL & VITAL Performance Optimization


Verilog RTL & Gate Performance Optimization

The Verilog RTL & Gate performance optimizer accelerates simulation of all types of Verilog designs, including designs with timing, gate-level designs, and designs with predominantly behavioral code. This optimizer integrates seamlessly with the standard simulation engine and does not require user intervention.

VHDL RTL & VITAL Performance Optimization

VHDL RTL & VITAL performance optimizer speeds up (in some cases up to 2 times) the simulation by blocking user access to signals that are not required for debugging. This kind of optimization is automatically performed in Active-HDL simulator during elaboration phase. There is no need to modify or recompile design sources to benefit from this VHDL simulation optimization technology.

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