Xilinx® SecureIP Support

Category : Simulation/Verification

Aldec simulators support the SecureIP methodology of IP delivery implemented in Xilinx tools. This option enables Aldec customers with VHDL only license to simulate SecureIP models without purchasing a separate Verilog license (which is required as these models leverage IEEE 1364-2005 encryption technology). In order to leverage this option, VHDL only customers must use the Xilinx Simulation Libraries coming with the installation of Active-HDL or Riviera-PRO, or download them from Aldec website.

Note: Xilinx ISE™ Design Suite has the Xilinx Simulation Library Compilation Wizard (COMPXLIB) tool that allows compiling libraries for the target Aldec simulator.

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