Design Flow Manager for All FPGA Vendors

Category : Project Management

The Design Flow Manager configures, constrains and executes simulation, synthesis and implementation tools for all devices from Altera®, Atmel®, Lattice®, Microsemi™ (Actel), Quicklogic®, Xilinx® and more in one integrated development environment. Active-HDL can be used both for vendor specific and vendor independent flows.

The Design Flow Manager automates simple, yet tedious tasks – for example after creating new files in Active-HDL, those files are automatically included in synthesis. The synthesized netlist is visible in Active-HDL and can be easily compiled and simulated. Likewise, place-and-route tools can be configured and launched from the Active-HDL GUI. The resulting netlist and SDF files are visible in Active-HDL.

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