Signal Agent (VHDL and Mixed Only)

Category : Debug and Analysis

The Signal Agent in VHDL allows monitoring and driving VHDL signals from any VHDL block. Signals do not have to be routed via the interface or declared in global packages. This is particularly useful in testbench development and design verification. The Signal Agent can also be used in mixed designs to drive Verilog objects anywhere in the design hierarchy directly from VHDL. It is possible to drive Verilog wires, integer and real values. It can also drive VHDL signals with values read from Verilog nets or registers.

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