Testbench Generation from State Diagram

Category : Code Generation Tools

An auxiliary verification tool built-in to Active-HDL that creates testbenches used to test the HDL code generated by the State Diagram Editor. For control units, a set of comprehensive testbenches can be produced automatically to cover all states and transitions defined on a state diagram created with Active-HDL. There are three strategies of testbench testing that can be set individually for specific needs in user-defined projects.

  • Strategy 1: creates a testbench containing a set of stimuli for state machine's inputs that is required to move through all states of the machine's state register.
  • Strategy 2: creates a testbench containing a set of stimuli for state machine's inputs that is required to move through all transitions of the machine's state register.
  • Strategy 3: creates a testbench containing a set of stimuli needed to test transitions from each state of the state machine to the Reset state the moment the Reset condition becomes TRUE
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