SystemC™ 2.3.1 IEEE 1666™/TLM 2.0

Category : Supported Standards

SystemC is a C library that extends C to enable hardware modeling. Although strictly a C class library, SystemC is sometimes viewed as being a language in its own right. One of the points of SystemC is to enable you to model and simulate things at a higher level of abstraction than RTL (Verilog, VHDL). 

 

SystemC is applied to system-level modeling, architectural exploration, performance modeling, software development, functional verification, and high-level synthesis. SystemC is often associated with Electronic system level (ESL) design, and with Transaction-level modeling (TLM). SystemC enables a top-down implementation where you start with a high-level architectural model and refine it down to the RTL level.

 

Aldec simulators provide direct support of SystemC in VHDL, Verilog and mixed designs - no additional coding is required to instantiate SystemC module in HDL or HDL block in SystemC.

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