Batch Mode Simulation/Regression (VSimSA)Category : Simulation/VerificationVSimSA is a standalone VHDL/Verilog simulation environment designed for batch processing. It consists of several separate programs and DLL libraries which make four basic modules: •VHDL compiler•Verilog compiler•Library management system•VHDL/Verilog simulation engine with command interpreterVSimSA works in command line mode independent of the Active-HDL or Riviera-PRO graphical user interface (GUI). The VSimSA simulator includes an interpreter of commands that are used to control the simulation and the entire VSimSA environment. The commands can be entered directly in interactive mode from the VSimSA simulator prompt or be placed in a macro file. The syntax of VSimSA commands is similar to that of the Aldec macro command language.