ALINT-PRO with Basic Rule Library

Category : Design Rule Checking

Aldec® ALINT-PRO™ is a design verification solution for RTL code written in VHDL, Verilog, and SystemVerilog. The solution performs static analysis based on RTL and SDC™ source files uncovering critical design issues early in the design cycle. Running ALINT-PRO before the RTL simulation and logic synthesis phases prevents design issues spreading into the downstream stages of design flow and reduces the number of iterations required to finish the design. ALINT-PRO features a well-designed, intuitive framework, which offers features for efficient design analysis.


ALINT-PRO with Basic Rule Library includes 120 Verilog and VHDL rules. A set of extra rule libraries are provided for comprehensive verification.


The following topics are covered by ALINT-PRO rule libraries:

  • Coding style and naming conventions
  • RTL and post-synthesis simulation mismatches
  • Optimal synthesis
  • Correct FSM descriptions 
  • Clocks and reset tree issues
  • Clock/reset domains crossings
  • Design for tests (DFT)
  • Coding for portability and reuse
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