ALINT with Basic Rule Library

Category : Design Rule Checking

Aldec® ALINT™ analyzes VHDL, Verilog and Mixed Language HDL code during compilation, prior to simulated or synthesized. It checks for compliance to user-selected, preset rules grouped into several categories. ALINT will mainly report same issues as a synthesis tool. But ALINT detects bugs at RTL level (during design creation) while synthesis tool does it during synthesis. ALINT includes Advanced Rule Management, Violation Summary/Viewing/Reporting, and configuration management applications.  ALINT with Basic Rule Library includes 95 Verilog and VHDL rules.
The following groups of rules are included:

  • Coding Style Rules
  • Design for Tests (DFT) Rules
  • Design Style Rules
  • Language Construct Rules
  • Simulation Rules
  • Synthesis Rules
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