Aldec and NEC reveal HLS shortcut at upcoming SoC Conference

Breaking through the growing design verification maze

Satyam Jani, Product Manager Software Division
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The University of California, Irvine (UCI) is popular for many things, but I recall during my school days that it was distinctly known among students for its underground tunnel network. The official story is that they were simply built to house heating and cooling pipes. Yet, the rumor persists that this complex maze of underground tunnels was constructed decades ago to provide safe passage for faculty members in case of student riots.


I’ll admit I would love to uncover these tunnels someday, unfortunately they have long been sealed off from curiosity seekers. I will, however, be at the UCI campus next week unraveling a different sort of maze for engineers attending the annual International SoC Conference. Aldec is once again a Platinum Sponsor for this popular academic conference, and this year I will be joined by NEC Corporation’s Dr. Wakabayashi to present a technical session:


FPGA+C-based HLS Can Outperform GPGPU (SIMD Processors) from the View Point of Compiler and Architecture  

Thursday, October 24, 2013 – SoC Conference - UCI - Calit2 Building


In this session, we’ll demonstrate the benefits of using FPGA+C-based flow from the GPGPU (SIMD processors) perspective. Recently, C-based high level synthesis flow has been used to design FPGAs for real time systems, such as in the financial area (High Frequency Trading), M2M (Multi-sensor), etc. High-level synthesis brings the paradigm shift by allowing designers to work at algorithmic level using ANSI-C and SystemC. We will use the real time example to show that FPGA+C-based high level synthesis flow can outperform GPGPU (SIMD processors) from the view point of compiler and architecture perspective.


In the end, no SoC validation ecosystem is complete without having hardware validation solution. High-level synthesis solution from NEC , combined with Aldec’s HES-7™ hardware validation solution, creates a powerful platform that allows prototyping of ASIC designs up to 96 million ASIC gates utilizing Xilinx™ Virtex®7 2000T FPGAs. For the embedded application developer, HES-7 also provides support for ARM® dual-core Cortex™-A9 MPCore™ leveraging Xilinx Zynq™, along with peripherals supporting media interfaces, memories and additional connectors to expand the development of a wide array of SoC applications.


To learn more about high-level synthesis and its benefits, please visit Aldec and NEC at the upcoming International SoC Conference, or visit

Satyam manages Aldec’s leading FPGA design entry and simulation tool – Active-HDL. He received his B.S. in Electronics Engineering from Sardar Patel University, India in 2003 and M.S in Electrical Engineering from NJIT, New Jersey in 2005.  His practical engineering experience includes areas in Solid state electronics, Digital Designing and functional verification. He has worked in wide range of engineering positions that include FPGA Design Engineer, Applications Engineer and Product Manager.


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