SCE-MI for SoC Verification

Transaction-level Interface Delivers Performance

Bill Jason P. Tomas, Product Engineer, Hardware Division
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Today’s System-on-Chip verification teams are moving up in the levels of abstraction to increase the degree of coverage in the system design. As designs grow larger, we start to see an increase in test time within our HDL simulations. Engineers can utilize Hardware-Assisted approaches such as simulation acceleration, transaction-level co-emulation, and prototyping to combat the growing simulation times of an RTL simulator. In this article, we'll dive much deeper into the transaction-level co-emulation methodology.

Co-Emulation is a transaction-level oriented Hardware-Assisted verification method, as opposed to event-based using simulation acceleration. Hardware and software communicate via messages, which can translate to hundreds of clock cycles in hardware, and conversely, hundreds of clocks cycles in HW can translate to a single message in software. The Standard for Co-Emulation Modeling Interface (SCE-MI) was developed by Accelera so that SoC designs can run at their full performance potential in hardware emulation platforms. This is done with a set of synthesizable transactions, which are bus functional models which translate high level messages to signal level interfaces.


Figure 1. Synthesizable transactors


SCE-MI provides three main interfaces: Macro-based, function-based, and pipes-based. The pipes-based model hasn't gained much attention from users because it is perceived as complicated and doesn't offer clear advantages over other models. For the sake of brevity, we'll omit a discussion of the pipes-based model here. Macro-based utilizes a set of defined macros to communicate between the software portion of the environment to the transactor implemented in hardware. These message ports utilize a dual-ready handshake which moves data between the hardware and software when both are ready. The SCE-MI infrastructure connects the macros to software proxies in software - and provides a C++ API which allows connecting high-level testbenches (C/C++/SystemC).


Table 1. Comparison of macro-based and function-based SCE-MI models


Function-based SCE-MI takes advantage of SystemVerilog Direct Programming Interface (DPI). In this interface the functional call, which is defined by the user, is the actual message call. This eliminates the pre-defined API, and allows the engineer to define their own API based on their verification environment. Functions are defined and called in their native languages - requiring very little training for a user to understand. In addition, the SystemVerilog DPI is already a standard found in the SystemVerilog LRM - and is supported in many 3rd party simulators.


Figure 2. The macro-based model


To learn more about how co-emulation infrastructure can benefit both hardware and software teams - allowing co-verification and early access to HW for software teams, please register to join me for the upcoming webinar: Hybrid SoC Verification and Validation Platform for Hardware and Software Teams - Sept. 26.. This webinar will cover several use cases of SCE-MI, and how Aldec’s Hardware-Assisted Verification solution, HES, can reduce verification time, cut costs, and get to tape-out faster.  Registrants will also receive access to a soon-to-be-released white paper on this topic.


Bill is responsible for Aldec Hardware Emulation and SoC / ASIC Prototyping. He received his B.S. in Computer Engineering from Auburn University in Alabama in 2011, and currently undertaking his M.S in Electrical Engineering with a focus on hardware emulation methodology and Built-In-Self-Test for high capacity FPGAs. He is also currently a graduate research assistant for the University of Nevada Systems and Integration laboratory studying Network-on-Chip BIST strategies. 


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