Company Newsroom Industry’s First use of TLM for the At-Speed Verification of a PCIe-Based Avionics Design Requiring DO-254 Compliance Release 2022/02/14 Productivity Through Methodology: Aldec Adds UVM Generator to Riviera-PRO™ Plus Updates Its OSVVM and UVVM Libraries Release 2021/11/16 New HES Board is Ideal for Prototyping and Emulating Medium to Large ASIC & SoC Designs Release 2021/08/16 New TySOM-M Series Targets Low Power, High Security Applications Release 2021/07/07 Aldec Launches HES-DVM Proto ‘Cloud Edition’ - Giving Engineers Easier Access to FPGA-based ASIC & SoC Prototyping Release 2021/06/02 Airborne System Design Assurance: Aldec Adds 60+ New HDL Rules to ALINT-PRO’s DO-254 Plug-In Release 2021/03/04 Powerful FPGA Design Creation and Simulation IDE Adds VHDL-2019 Support & OSVVM Enhancements Release 2021/01/20 RECENT NEWS VHDL-2019プロテクトタイプによるVHDLの検証機能の向上 Release MAR 29, 2022アルデックはロシアにおけるすべてのEDA販売・代理店取引を停止しますRelease MAR 14, 2022業界初、DO-254コンプライアンスを必要とするPCIeベースのアビオニクスデザインのアットスピード検証にTLMを使用In the News JAN 13, 2022メソドロジーによる生産性の向上：アルデックは、Riviera-PRO™にUVMジェネレータを追加し、OSVVMおよびUVVMライブラリを更新 Release NOV 16, 2021中規模から大規模ASIC/SoCデザインのプロトタイピングおよびエミュレーションに最適な新しいHESボードRelease JUL 19, 2021低消費電力、高セキュリティアプリケーションをターゲットにした新しいTySOM-MシリーズRelease JUL 07, 2021 view all news RECENT YOUTUBE VIDEOS How to Connect Partition's Logical Connections on Multi-FPGA Prototyping Board Using HES-DVM on AWS How to Run User Guided Multi FPGA Partitioning Using Aldec's HES-DVM on the AWS Cloud How to Prepare HES DVM Compatible Custom Board Files Using Board Compiler Tool How to Automatically Partition an ASIC Design into Multiple FPGAs Using HES DVM view all videos RECENT BLOG ARTICLES The Convergence of Emulation and Prototyping Development of real-time SDR systems with Aldec HES Performing cross spectrum video processing on a TySOM-3 board Matching image data between the thermal and visible spectrum for non-contact human body temperature screening helps in the fight against COVID-19 How does the Mars Perseverance rover benefit from FPGAs as the main processing units? FPGAs on Mars SynthHESer - Aldec’s New Synthesis Tool view all articles UPCOMING EVENTS FPGA Design/Verification Best-Practices for Quality and EfficiencyPart 4: Code, Functional and Specification Coverage (EU)ウェブセミナー MAY 19, 2022FPGA Design/Verification Best-Practices for Quality and EfficiencyPart 4: Code, Functional and Specification Coverage (US)ウェブセミナー MAY 19, 2022Better FPGA Verification with VHDLPart 1: OSVVM - Leading Edge Verification for the VHDL Community (EU)ウェブセミナー MAY 26, 2022Better FPGA Verification with VHDLPart 1: OSVVM - Leading Edge Verification for the VHDL Community (US)ウェブセミナー MAY 26, 2022 view all events
