Company Newsroom Industry’s First use of TLM for the At-Speed Verification of a PCIe-Based Avionics Design Requiring DO-254 Compliance Release 2022/02/14 Productivity Through Methodology: Aldec Adds UVM Generator to Riviera-PRO™ Plus Updates Its OSVVM and UVVM Libraries Release 2021/11/16 New HES Board is Ideal for Prototyping and Emulating Medium to Large ASIC & SoC Designs Release 2021/08/16 New TySOM-M Series Targets Low Power, High Security Applications Release 2021/07/07 Aldec Launches HES-DVM Proto ‘Cloud Edition’ - Giving Engineers Easier Access to FPGA-based ASIC & SoC Prototyping Release 2021/06/02 Airborne System Design Assurance: Aldec Adds 60+ New HDL Rules to ALINT-PRO’s DO-254 Plug-In Release 2021/03/04 Powerful FPGA Design Creation and Simulation IDE Adds VHDL-2019 Support & OSVVM Enhancements Release 2021/01/20 RECENT NEWS Versal ACAPのような複雑なSoC FPGAのシミュレーションには何が必要ですか？In the News FEB 08, 2024Aldec @ DAC 2023：FPGAおよびSoC向け設計検証ツールとソリューションを紹介Release JUN 26, 2023Riviera-PROがAMD® Versal™ ACAPデザインのシステムシミュレーションをサポートRelease JUN 14, 2023航空電子機器業界で高まる TLM のニーズIn the News MAY 18, 2023アルデックとタレスがCertification Together International Conference 2023で共同発表Release MAY 01, 2023アルデック、マイクロチップ社のFPGAおよびSoC FPGA設計のための自動スタティックリンティングとCDC解析をリリースRelease FEB 06, 2023 view all news RECENT YOUTUBE VIDEOS VHDL 2019 Just the New Stuff Part 1: Interfaces, Conditional Analysis, File IO, & New Environment HW/SW Co-simulation solution for Zynq SoC based systems using Riviera-PRO and QEMU Riviera PRO Product Overview How to Connect Partition's Logical Connections on Multi-FPGA Prototyping Board Using HES-DVM on AWS view all videos RECENT BLOG ARTICLES Scalable Cloud-based CI/CD HDL Verification Environment Enhance Your Verification Workflow with Azure, VUnit, and Riviera-PRO Navigating VUnit: A Practical Guide to Modifying Testing Approaches Speeding Up Simulation with VUnit for Parallel Testing Introduction to VUnit FPGA Design Verification in a Nutshell view all articles UPCOMING EVENTS HDLRegression – Automated Regression Testing for VHDL/Verilog (US)ウェブセミナー AUG 21, 2025HDLRegression – Automated Regression Testing for VHDL/Verilog (EU)ウェブセミナー AUG 21, 2025 view all events
