Company Newsroom Aldec’s TySOM Family of Embedded System Development Solutions Now Supports Xilinx PYNQ (Python Productivity for Zynq) Release 2020/10/21 Aldec Provides Static Verification for RISC-V Designs with the latest release of ALINT-PRO Release 2020/07/22 Aldec Introduces Hardware Assisted RTL Simulation Acceleration for Microchip FPGA Designs Release 2020/11/03 New to Riviera-PRO™: VHDL-2019 Support and a Versatile UVM Registers Window Release 2020/06/24 Aldec Adds Customizable Tool Qualification Data Package to ALINT-PRO™ for DO-254 Projects Release 2020/06/30 RECENT NEWS SemiWiki: Aldec Adds Simulation Acceleration for Microchip FPGAsIn the News NOV 10, 2020アルデック、Microchip FPGA設計のためのハードウェア支援型RTLシミュレーションアクセラレーションを発表Release NOV 03, 2020アルデックの組込みシステム開発ソリューションのTySOMファミリが、Xilinx PYNQ（Python Productivity for Zynq）をサポートしましたRelease OCT 21, 2020アルデックのTySOM組込み開発キットがAWS IoT Greengrassに認証されましたRelease AUG 05, 2020アルデックは、ALINT-PROの最新リリースでRISC-Vデザインのスタティック検証を提供Release JUL 22, 2020Aldec @ DAC 2020: RISC-Vの検証メソドロジとソリューションを紹介しますRelease JUL 15, 2020 view all news RECENT YOUTUBE VIDEOS PCIe 5 Simulation Verification Demonstration Unboxing TySOM-3A-ZU19EG Embedded Development Board DAC 2019 Demo - Hybrid Co Emulation with ARM Hardware Model DAC 2019 Demo - SoC Simulation Environment for Mixed Signal Designs view all videos RECENT BLOG ARTICLES SynthHESer - Aldec’s New Synthesis Tool Linting RISC-V designs with ALINT-PRO Enabling TySOM Zynq-based Embedded Development Board for AWS IoT Greengrass Qualified Zynq SoC Dev Board for IoT Greengrass Connecting Emulated Design to External PCI Express Device Is your Verification plan pulling you in multiple directions? Try FSM Coverage A quick look into FSM Coverage view all articles UPCOMING EVENTS Debugging Multi-Core Designs using Vitis + Aldec Riviera-PRO Co-Simulation for Zynq US+ MPSoC (US)ウェブセミナー DEC 03, 2020Debugging Multi-Core Designs using Vitis + Aldec Riviera-PRO Co-Simulation for Zynq US+ MPSoC (EU)ウェブセミナー DEC 03, 2020RISC-V Summit業界イベント DEC 08, 2020 view all events
