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Name Products Type Action
ASIC プロトタイピング - Xilinxとの共著   
本論文では、最新のVirtex-7デバイスおよびVirtex-7 2000Tを2つ搭載したAldec HES-7プロトタイピング・ボードに注目し、FPGAベースのプロトタイピングを使用したASIC検証の可能性について説明しています。また、最も一般的なパーティショニングの問題と解決策について記載されています。
HES-DVM, HES™ Boards ホワイトペーパー
ASICおよびFPGAデザインでのリセットとリセットドメインクロッシング   
このホワイトペーパーでは、ASICおよびFPGAデザインのリセット関連の問題、およびよく使用される安全なリセット実装についての設計手法の概要について解説します。さらにリセットドメインクロッシング効果とその影響を緩和する方法についても解説します。LINTツールは設計者にとって、リセットとリセットドメインクロッシング検証に役立ちます。
ALINT-PRO ホワイトペーパー
Accelerate SoC Simulation Time of Newer Generation FPGAs   
Comprehensive verification that can be provided by HDL simulators is good, but not ideal. What is necessary is a faster, safer, and more thorough verification environment that combines the robustness of an HDL simulator with the speed of FPGA prototyping boards. The goal is to put together the power of these two verification methodologies into one platform.
HES-DVM ホワイトペーパー
Aldec DO-254 Solutions Blueprint   
The Federal Aviation Administration (FAA) recognizes the use of commonly used tools for FPGA design and verification such as RTL Simulator, Synthesis, Place & Route and Static Timing Analysis. For DAL A and B FPGAs, the FAA also recognizes other tools that improve design, verification, traceability and project management including Requirements Management, Traceability, Tests Management, Design Rule Checker, Clock Domain Crossings (CDC) Analysis, Code Coverage and FPGA Physical Test Systems.
Active-HDL, ALINT-PRO, Spec-TRACER, DO-254/CTS ホワイトペーパー
Automated ASIC Regressions With Aldec Server Farm Manager   
Abstract: Aldec's Server Farm Manager (SFM) addresses ASIC regression testing issues for the fast, cost effective and high quality ASIC design verification.
Active-HDL ホワイトペーパー
Clarifying Language Methodology Confusion   
Abstract: Engineers working on modern, large FPGA designs face multiple challenges: changing languages, methodologies and tools implementing them. The fact that many designs now contain both hardware and software only adds to the confusion. This document tries to clarify the situation.
Active-HDL ホワイトペーパー
Concurrent FPGA-PCB Design within an Integrated Design Environment   
The increasing adoption of large, high-pin-count and high-speed FPGA devices means that right-first-time printed circuit board (PCB) design practices are more essential than ever for ensuring correct system operation. Typically, the PCB design takes place concurrently with the design and programming of the FPGA. Signal and pin assignments are initially made by the FPGA designer, and the board designer must correctly transfer these assignments to the symbols used in their system circuit schematics and board layout. As the board design progresses, pin reassignments may be needed to optimize the PCB layout. These reassignments must in turn be relayed back to the FPGA designer so that the new assignments can be processed through updated placement and routing of the FPGA design. To overcome these challenges, Zuken and Aldec provide an integrated design environment to support these design flows.
Active-HDL ホワイトペーパー
DO-254 Requirements Traceability   
DO-254 enforces a strict requirements-driven process for the development of commercial airborne electronic hardware. For DO-254, requirements must drive the design and verification activities, and requirements traceability helps to ensure this. This paper explains the rationale behind requirements traceability including its purpose and resulting benefits when done correctly.
Spec-TRACER ホワイトペーパー
DO-254 Tool Qualification Process Guidance for Active-HDL Code Coverage   
The purpose of the document is to Guide the Qualification Process for Active-HDL Code Coverage tool.
DO-254/CTS ホワイトペーパー
DO-254: Increasing Verification Coverage by Test   
Verification coverage by test is essential to satisfying the objectives of DO-254. However, verification of requirements by test during final board testing is challenging and time-consuming. This white paper explains the reasons behind these challenges, and provides recommendations how to overcome them. The recommendations center around Aldec’s unique device testing methodology that can significantly increase verification coverage by test.
DO-254/CTS ホワイトペーパー
Debugging SCE-MI Co-Emulation in Riviera-PRO   
Abstract: Debugging a design during emulation with a high level of visibility can be a challenge. This paper presents Aldec’s solution to this problem; a debugging environment for SCE-MI co-emulation that provides 100% signal visibility of the design running in an FPGA-based emulator. Debug probes captured intelligently from emulator retain original signals names and hierarchy paths to provide true RTL view of design in emulation.
Riviera-PRO, HES-DVM ホワイトペーパー
Designing UVM Testbench for Simulation and Emulation of Network-on-Chip Design   
Universal Verification Methodology (UVM) is one of the most popular approaches in using transactional testbench environment. The growth of SoC designs forces design and verification teams to use emulation as a way to speed-up verification process. Standard CoEmulation Modeling Interface (SCE-MI) provides ways to connect emulated design with transactional testbench. This paper describes how to use SCE-MI to create UVM test environment that is ready for both simulation and emulation.
HES-DVM ホワイトペーパー
Embedded Systems Verification   
Abstract: As the number of mobile and personal applications grows, usage of embedded processors becomes a necessity. New FPGA devices with so called soft or hard processor cores enable fast migration from the FPGA-only to the SoC applications and projects. This affects not only the hardware alone, but also the tools supporting the latest FPGA devices for SoC designers. Such tools are discussed within this document.
Active-HDL ホワイトペーパー
Enhancing VHDL Designs with Embedded PSL   
Abstract: PSL (Property Specification Language) is the easiest introduction to the world of design properties, assertions and coverage points to anybody familiar with VHDL (VHSIC Hardware Description Language). The designer of a digital circuit has the best understanding of the operation of the circuit, which makes her or him the best person to define properties that will fire assertion messages in case of incorrect design behavior during simulation or provide valuable feedback to the testbench creator by showing that all desired behaviors were covered during verification. For this reason, the use of embedded PSL properties and assertions is highly beneficial to the engineers and makes their designs better.
Active-HDL ホワイトペーパー
Enhancing Verilog Designs with Embedded PSL   
Abstract: PSL (Property Specification Language) is one of the easiest introductions to the world of design properties, assertions and coverage points to anybody familiar with Verilog HDL. The designer of a digital circuit has the best understanding of the operation of the circuit, which makes her or him the best person to define properties that will fire assertion messages in case of incorrect design behavior during simulation or provide valuable feedback to the testbench creator by showing that all desired behaviors were covered during verification. For this reason, the use of embedded PSL properties and assertions is highly beneficial to the engineers and makes their designs better.
Active-HDL ホワイトペーパー
Enhancing Verilog Designs with SVA   
Abstract: SVA (SystemVerilog Assertions) language is one of the easiest introductions to the world of design properties, assertions and coverage points to anybody familiar with Verilog HDL. The designer of a digital circuit has the best understanding of the operation of the circuit, which makes her or him the best person to define properties that will fire assertion messages in case of incorrect design behavior during simulation or provide valuable feedback to the testbench creator by showing that all desired behaviors were covered during verification. For this reason, the use of SVA properties and assertions directly in the design code is highly beneficial to the engineers and makes their designs better.
Active-HDL ホワイトペーパー
FPGAデザインフローの社内標準化   
顧客の要求や技術力が高まるにつれ、ハードウェア およびソフトウェア設計の複雑度も増加している。一方で開発期間は、新規デザインの寿命と同様に短くなっている。これら全ての要求を満たすためには、設計プロセスに対する新しいアプローチが必要となる。
Active-HDL ホワイトペーパー
FPGA世界におけるクロックドメインクロッシング   
クロックドメインクロッシング(CDC)の問題により、ASICおよびFPGAデバイスで多大な障害が発生しています。FPGAの複雑さと性能が向上するにつれて、CDCの問題がデザイン機能に与える影響はさらに大きくなっています。本紙では、CDCの問題とFPGAデザインのソリューションについて解説します。XilinxおよびIntel FPGAデバイスの実例とともに、さまざまなデザイン手法を紹介しています。 さらに重要なことに、本紙では信頼性の高いFPGAデザインの最も重要なCDCのガイドラインについてまとめています。
ALINT-PRO ホワイトペーパー
Finding CDC Issues Before They Find You: Advanced CDC Verification for DO-254 Compliance   
Clock domain crossings (CDCs) in FPGAs represent a probabilistic opportunity for failure. Functional simulation and static timing analysis tools are insufficient. Finding and addressing metastability and data incoherence around CDCs require static and dynamic analysis of FPGA designs. Aldec ALINT-PRO-CDC provides enhanced confidence that CDCs are located and fully mitigated.
ALINT-PRO ホワイトペーパー
HDL Simulation Acceleration Solution for Microchip FPGA Designs   
Mission-critical FPGA designs for space and radar applications continue to increase in complexity, such that they require a comprehensive and robust verification environment. There are hardware-in-the-loop solutions in the market that utilize FPGA boards, but when it comes to establishing functional coverage and debugging the custom logic, users would typically need to go back to HDL simulation. As a result, HDL simulations are becoming excessive and they have become the primary bottleneck when it comes to verification. In this paper we will describe a solution that can accelerate HDL simulation for the system FPGA design that includes the custom logic and reused IP Cores where the testbench executes in the simulator and the synthesizable parts of the design is implemented in a Microchip FPGA board.
Riviera-PRO, HES-DVM, HES™ Boards ホワイトペーパー
49 results (page 1/3)
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