Aldec Design and Verification Blog

Trending Articles
Versal ACAP Simulation Challenges

The electronics industry is all about optimization, and always has been. For example, you might think of system on chip (SoC) as a relatively recent term, coined this century. However, many regard the silicon that appeared in digital watches in the 1970s as constituting a system on a chip, ...

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Verification Effectiveness with Riviera-PRO: SystemVerilog Randomized Layered Testbench
Understanding SystemVerilog Layered Testbench

In this blog, I will discuss randomized layered testbenches used in SystemVerilog. We need to understand why we need it,...

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ARM Cortex SoC Prototyping Platform
for Industrial Applications

Modern industrial systems are faced with many key design challenges including: system complexity, real-time performance requirements, evolving standards, and rising costs. ASIC prototyping platforms, such as Aldec HES-7™, provide a platform for designers to implement and verify functionality of...

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Using Plots for HDL Debugging
A Powerful Alternative to Traditional Waveforms

The most commonly used approach to analyzing objects in an HDL design is based on well-known digital waveforms available with any commercial simulator today. Such a time domain representation of data with respect to time, allows verifying many parameters of a designed digital system, but it may not be efficient for...

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Fast Track™ to SystemVerilog for Verilog Users
Aldec’s Latest Free Online Training

Many experienced Verilog users tend to ignore SystemVerilog - mainly because high-end verification features of the new language are getting the majority of the  attention in the press, and at conferences and trade shows. Those users may not realize that there are many SystemVerilog features that are very useful for...

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Those Pesky SystemVerilog Interfaces...

SystemVerilog introduced numerous ideas new to Verilog programmers. Some of them enhanced hardware descriptions (e.g. always_ff block), some were meant to enhance verification (e.g. classes) and some were cross-over enhancements that can be used in many different contexts. SystemVerilog interface...

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Fastest Co-Simulation Interfaces
For MATLAB®, Simulink®, SystemVue®

Aldec Riviera-PRO™ offers the fastest direct co-simulation interfaces with MathWorks MATLAB® & Simulink® and Agilent SystemVue®, enabling multi-domain electronic system-level (ESL) design flow for DSP, RF, and FPGA/ASIC design....

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Shaping the Future of ASIC/FPGA DSP Design Flow
Take our survey

Aldec is conducting a brief survey through April 30, 2013, to better address the challenges and requirements faced by DSP designers in the field. As a thank you, a random drawing will be held among survey participants to receive a $100 Amazon giftcard...

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