Aldec Design and Verification Blog Trending Articles Scalable Cloud-based CI/CD HDL Verification Environment Navigating VUnit: A Practical Guide to Modifying Testing Approaches Speeding Up Simulation with VUnit for Parallel Testing Introduction to VUnit FPGA Design Verification in a Nutshell Versal ACAP Simulation Challenges Real-time SDR system with TySOM All Categories Corporate DO-254 Compliance Embedded Solutions Emulation/Acceleration FPGA Design Functional Verification High Performance Computing Requirements Management SoC and ASIC Prototyping SoC Design and Validation Specialized Applications Versal ACAP Simulation Challenges The electronics industry is all about optimization, and always has been. For example, you might think of system on chip (SoC) as a relatively recent term, coined this century. However, many regard the silicon that appeared in digital watches in the 1970s as constituting a system on a chip, ... Tags:Embedded,FPGA,Riviera-PRO,FPGA Simulation,Functional Verification,safety-critical,SystemC,SystemVerilog,VHDL,UVM Like(0) Comments (0) Read more Integrating SystemVerilog and SCE-MI for Faster Emulation Speed Developing your own Emulation API In the last SCE-MI article, we discussed how SCE-MI macro-based infrastructures can speedup SoC design verification time. In SCE-MI 2.1, Accelera introduced a ‘function-based’ infrastructure... Tags:Emulation,SoC,SystemC,SystemVerilog,Verification Like(3) Comments (0) Read more The WHAT is mandatory but the HOW is entirely optional Intro to High Level Synthesis You look confused. Perhaps I owe you an explanation. Anyone familiar with hardware design flow knows that it starts with specification and ends with implementation. The specification in this flow is the “What” – it defines what needs to be designed.... Tags:Design,SoC,SystemC,Validation,Verification Like(1) Comments (0) Read more The Magic of CyberWorkBench Why you should take a closer look My first encounter with NEC’s CyberWorkBench (CWB) was in 2003 while attending DAC. Like most people, I was surprised to see a big Japanese company offering EDA tools.... Tags:Design,SoC,SystemC,Validation,Verification Like(2) Comments (0) Read more ASIC/FPGA High Level Synthesis Solution from NEC CyberWorkBench joins Aldec’s Verification Ecosystem Aldec (tried to) quietly introduce our new friends from NEC Japan for the first time at DAC this year. They joined us in our booth in Austin and were soon the life of the party as many people were eager to learn... Tags:Design,SoC,Verification,SystemC,Validation Like(2) Comments (0) Read more
