Aldec Blog/News RSS Feed https://www.aldec.com Aldec News RSS Feed News: 2018-07-19 https://www.aldec.com/jp/company/news/2018-07-19/405 https://www.aldec.com/jp/company/news/2018-07-19/405 Thu, 19 Jul 2018 00:00:00 -0700 Enhanced early static checks of Finite State Machines and Xilinx IP-based designs News: 2018-06-07 https://www.aldec.com/jp/company/news/2018-06-07/404 https://www.aldec.com/jp/company/news/2018-06-07/404 Thu, 07 Jun 2018 00:00:00 -0700 Aldec @ DAC 2018: Presenting Innovative SoC Design & Verification Methodologies Blog: 2018-05-30 https://www.aldec.com/jp/company/blog/172--the-power-of-pcie-in-performance-based-fpga-world https://www.aldec.com/jp/company/blog/172--the-power-of-pcie-in-performance-based-fpga-world Wed, 30 May 2018 00:00:00 -0700 The Power of PCIe in Performance-based FPGA World Blog: 2018-05-30 https://www.aldec.com/jp/company/blog/171--hwsw-co-simulation-for-soc-fpga-designs https://www.aldec.com/jp/company/blog/171--hwsw-co-simulation-for-soc-fpga-designs Wed, 30 May 2018 00:00:00 -0700 HW/SW Co-Simulation for SoC FPGA designs Blog: 2018-05-29 https://www.aldec.com/jp/company/blog/170--problems-accessing-registers-see-how-uvm-ral-can-help https://www.aldec.com/jp/company/blog/170--problems-accessing-registers-see-how-uvm-ral-can-help Tue, 29 May 2018 00:00:00 -0700 Problems Accessing Registers? – See how UVM RAL can help News: 2018-05-08 https://www.aldec.com/jp/company/news/2018-05-08/400 https://www.aldec.com/jp/company/news/2018-05-08/400 Tue, 08 May 2018 00:00:00 -0700 アルデック、Riviera-PRO™に自動UVMレジスタジェネレータ、ユニットリンティング、初期のVHDL 2018拡張機能の3つの機能強化を実施 News: 2018-05-02 https://www.aldec.com/jp/company/news/2018-05-02/399 https://www.aldec.com/jp/company/news/2018-05-02/399 Wed, 02 May 2018 00:00:00 -0700 アルデックとTamba Networks、The Trading Show 2018でUltraScale+ FPGA向けの超低レイテンシのEthernetソリューションをリリース Blog: 2018-04-30 https://www.aldec.com/jp/company/blog/169--the-race-to-zero-latency-for-high-frequency-trading https://www.aldec.com/jp/company/blog/169--the-race-to-zero-latency-for-high-frequency-trading Mon, 30 Apr 2018 00:00:00 -0700 The Race to Zero Latency for High Frequency Trading Blog: 2018-04-27 https://www.aldec.com/jp/company/blog/167--fpgas-vs-gpus-for-machine-learning-applications-which-one-is-better https://www.aldec.com/jp/company/blog/167--fpgas-vs-gpus-for-machine-learning-applications-which-one-is-better Fri, 27 Apr 2018 00:00:00 -0700 FPGA vs GPU for Machine Learning Applications: Which one is better? Blog: 2018-04-27 https://www.aldec.com/jp/company/blog/168--verification-effectiveness-with-riviera-pro-systemverilog-randomized-layered-testbench https://www.aldec.com/jp/company/blog/168--verification-effectiveness-with-riviera-pro-systemverilog-randomized-layered-testbench Fri, 27 Apr 2018 00:00:00 -0700 Verification Effectiveness with Riviera-PRO: SystemVerilog Randomized Layered Testbench News: 2018-04-18 https://www.aldec.com/jp/company/news/2018-04-18/401 https://www.aldec.com/jp/company/news/2018-04-18/401 Wed, 18 Apr 2018 00:00:00 -0700 SemiWiki: RDC - A Cousin To CDC News: 2018-04-11 https://www.aldec.com/jp/company/news/2018-04-11/398 https://www.aldec.com/jp/company/news/2018-04-11/398 Wed, 11 Apr 2018 00:00:00 -0700 アルデックのHES UltraScale+リコンフィギュラブル・アクセラレータにNorthwest LogicのPCI Expressコアを搭載して実証済みのPCI Expressソリューションを提供 Blog: 2018-03-26 https://www.aldec.com/jp/company/blog/166--understanding-the-inner-workings-of-uvm-part-3 https://www.aldec.com/jp/company/blog/166--understanding-the-inner-workings-of-uvm-part-3 Mon, 26 Mar 2018 00:00:00 -0700 Understanding the inner workings of UVM - Part 3 Blog: 2018-03-26 https://www.aldec.com/jp/company/blog/165--do-i-really-need-a-commercial-simulator https://www.aldec.com/jp/company/blog/165--do-i-really-need-a-commercial-simulator Mon, 26 Mar 2018 00:00:00 -0700 Do I really need a commercial simulator? Blog: 2018-03-15 https://www.aldec.com/jp/company/blog/164--systemverilog-functional-coverage-in-a-nutshell https://www.aldec.com/jp/company/blog/164--systemverilog-functional-coverage-in-a-nutshell Thu, 15 Mar 2018 00:00:00 -0700 SystemVerilog Functional Coverage in a Nutshell News: 2018-03-12 https://www.aldec.com/jp/company/news/2018-03-12/402 https://www.aldec.com/jp/company/news/2018-03-12/402 Mon, 12 Mar 2018 00:00:00 -0700 SemiWiki: Clock Domain Crossing in FPGA Blog: 2018-02-28 https://www.aldec.com/jp/company/blog/160--trace-your-assertions https://www.aldec.com/jp/company/blog/160--trace-your-assertions Wed, 28 Feb 2018 00:00:00 -0800 Trace Your Assertions Blog: 2018-02-28 https://www.aldec.com/jp/company/blog/161--unit-linting-an-easy-way-to-prevent-code-review-issues https://www.aldec.com/jp/company/blog/161--unit-linting-an-easy-way-to-prevent-code-review-issues Wed, 28 Feb 2018 00:00:00 -0800 Unit Linting: An easy way to prevent code review issues Blog: 2018-02-27 https://www.aldec.com/jp/company/blog/159--how-to-develop-an-fpga-based-embedded-vision-application-for-adas-series-of-blogs-part-1 https://www.aldec.com/jp/company/blog/159--how-to-develop-an-fpga-based-embedded-vision-application-for-adas-series-of-blogs-part-1 Tue, 27 Feb 2018 00:00:00 -0800 How to develop an FPGA-based Embedded Vision application for ADAS, series of blogs – Part 1 News: 2018-02-21 https://www.aldec.com/jp/company/news/2018-02-21/396 https://www.aldec.com/jp/company/news/2018-02-21/396 Wed, 21 Feb 2018 00:00:00 -0800 アルデック、Embedded World 2018でSoC FPGA向けベリフィケーション・スペクトラムを展示