Aldec Blog/News RSS Feed https://www.aldec.com Aldec News RSS Feed News: 2019-05-15 https://www.aldec.com/jp/company/news/2019-05-15/418--aldec-dac-2019-celebrating-its-35th-anniversary-and-focusing-on-design-acceleration-co-verification-and-mixed-signal https://www.aldec.com/jp/company/news/2019-05-15/418--aldec-dac-2019-celebrating-its-35th-anniversary-and-focusing-on-design-acceleration-co-verification-and-mixed-signal Wed, 15 May 2019 00:00:00 -0700 Aldec @ DAC 2019: Celebrating its 35th Anniversary and focusing on design acceleration, co-verification and mixed-signal News: 2019-04-01 https://www.aldec.com/jp/company/news/2019-04-01/416 https://www.aldec.com/jp/company/news/2019-04-01/416 Mon, 01 Apr 2019 00:00:00 -0700 チームのハードウェアライフサイクルデータ管理 Blog: 2019-02-26 https://www.aldec.com/jp/company/blog/174--no-risk-no-fun https://www.aldec.com/jp/company/blog/174--no-risk-no-fun Tue, 26 Feb 2019 00:00:00 -0800 No Risk No Fun News: 2019-02-26 https://www.aldec.com/jp/company/news/2019-02-26/415--latest-tysom-kit-accelerates-the-development-of-ai-dnn-and-other-algorithm-acceleration-dependent-applications-plus-aids-soc-prototyping https://www.aldec.com/jp/company/news/2019-02-26/415--latest-tysom-kit-accelerates-the-development-of-ai-dnn-and-other-algorithm-acceleration-dependent-applications-plus-aids-soc-prototyping Tue, 26 Feb 2019 00:00:00 -0800 最新のTySOMキットは、AI、DNN、およびその他のアルゴリズムアクセラレーションに依存するアプリケーションの開発を促進し、SoCプロトタイピングを支援します News: 2019-01-22 https://www.aldec.com/jp/company/news/2019-01-22/414 https://www.aldec.com/jp/company/news/2019-01-22/414 Tue, 22 Jan 2019 00:00:00 -0800 AldecはFPGAのデザインプロトタイピングと新しいHES Proto-AXIによってプロトタイプテストを容易にします News: 2019-01-14 https://www.aldec.com/jp/company/news/2019-01-14/413--aldec-shortens-time-of-asic-design-prototype-bring-up-in-fpga-with-hes-dvm-proto-mode https://www.aldec.com/jp/company/news/2019-01-14/413--aldec-shortens-time-of-asic-design-prototype-bring-up-in-fpga-with-hes-dvm-proto-mode Mon, 14 Jan 2019 00:00:00 -0800 アルデックがHES-DVMプロトモードでFPGAのASIC設計プロトタイプ立ち上げの時間を短縮 News: 2018-11-13 https://www.aldec.com/jp/company/news/2018-11-13/412 https://www.aldec.com/jp/company/news/2018-11-13/412 Tue, 13 Nov 2018 00:00:00 -0800 VHDL 2018のサポートと強化された自動化 - アルデック、Riviera-PRO™にVHDL標準1076-2018の拡張と自動カバレッジモデル生成を追加 News: 2018-10-22 https://www.aldec.com/jp/company/news/2018-10-22/411 https://www.aldec.com/jp/company/news/2018-10-22/411 Mon, 22 Oct 2018 00:00:00 -0700 Aldec’s “Hardware and Software Co-verification in Hybrid Simulation and Emulation Environment with QEMU” DVCon Europe tutorial to demonstrate how engineers can obtain a holistic view over their SoC design News: 2018-10-15 https://www.aldec.com/jp/company/news/2018-10-15/410 https://www.aldec.com/jp/company/news/2018-10-15/410 Mon, 15 Oct 2018 00:00:00 -0700 A View from Above - Aldec adds a ‘Bird’s Eye View’ function to its growing portfolio of ADAS FPGA-based reference designs for its TySOM-3-ZU7EV embedded development kit - enabling automotive engineers to fast-track their HW/SW development and verification activities News: 2018-10-15 https://www.aldec.com/jp/company/news/2018-10-15/409--visible-benefits-aldec-makes-available-a-4k-ultra-hd-image-pass-through-reference-design-for-users-of-its-xilinx-zynq-ultrascale-mpsoc-embedded-development-kit-tysom-3-zu7ev https://www.aldec.com/jp/company/news/2018-10-15/409--visible-benefits-aldec-makes-available-a-4k-ultra-hd-image-pass-through-reference-design-for-users-of-its-xilinx-zynq-ultrascale-mpsoc-embedded-development-kit-tysom-3-zu7ev Mon, 15 Oct 2018 00:00:00 -0700 Visible Benefits Blog: 2018-08-28 https://www.aldec.com/jp/company/blog/173--what-is-birds-eye-view-adas-application-and-how-to-develop-this-using-zynq-ultrascale-mpsoc-fpga https://www.aldec.com/jp/company/blog/173--what-is-birds-eye-view-adas-application-and-how-to-develop-this-using-zynq-ultrascale-mpsoc-fpga Tue, 28 Aug 2018 00:00:00 -0700 What is Bird’s Eye View ADAS Application and How to Develop This Using Zynq® UltraScale+™ MPSoC FPGA? News: 2018-08-08 https://www.aldec.com/jp/company/news/2018-08-08/408 https://www.aldec.com/jp/company/news/2018-08-08/408 Wed, 08 Aug 2018 00:00:00 -0700 SemiWiki: RAL, Lint and VHDL-2018 News: 2018-07-20 https://www.aldec.com/jp/company/news/2018-07-20/406--aldec-to-present-at-the-6th-china-national-fpga-industry-development-forum https://www.aldec.com/jp/company/news/2018-07-20/406--aldec-to-present-at-the-6th-china-national-fpga-industry-development-forum Fri, 20 Jul 2018 00:00:00 -0700 Aldec to Present at the 6th China National FPGA Industry Development Forum News: 2018-07-19 https://www.aldec.com/jp/company/news/2018-07-19/405 https://www.aldec.com/jp/company/news/2018-07-19/405 Thu, 19 Jul 2018 00:00:00 -0700 有限ステートマシンと Xilinx IPベースデザインの設計早期におけるスタティック解析の強化 News: 2018-06-11 https://www.aldec.com/jp/company/news/2018-06-11/407 https://www.aldec.com/jp/company/news/2018-06-11/407 Mon, 11 Jun 2018 00:00:00 -0700 SemiWiki: RAL, Lint and VHDL-2018 News: 2018-06-07 https://www.aldec.com/jp/company/news/2018-06-07/404 https://www.aldec.com/jp/company/news/2018-06-07/404 Thu, 07 Jun 2018 00:00:00 -0700 Aldec @ DAC 2018: Presenting Innovative SoC Design & Verification Methodologies Blog: 2018-05-30 https://www.aldec.com/jp/company/blog/172--the-power-of-pcie-in-performance-based-fpga-world https://www.aldec.com/jp/company/blog/172--the-power-of-pcie-in-performance-based-fpga-world Wed, 30 May 2018 00:00:00 -0700 The Power of PCIe in Performance-based FPGA World Blog: 2018-05-30 https://www.aldec.com/jp/company/blog/171--hwsw-co-simulation-for-soc-fpga-designs https://www.aldec.com/jp/company/blog/171--hwsw-co-simulation-for-soc-fpga-designs Wed, 30 May 2018 00:00:00 -0700 HW/SW Co-Simulation for SoC FPGA designs Blog: 2018-05-29 https://www.aldec.com/jp/company/blog/170--problems-accessing-registers-see-how-uvm-ral-can-help https://www.aldec.com/jp/company/blog/170--problems-accessing-registers-see-how-uvm-ral-can-help Tue, 29 May 2018 00:00:00 -0700 Problems Accessing Registers? – See how UVM RAL can help News: 2018-05-08 https://www.aldec.com/jp/company/news/2018-05-08/400 https://www.aldec.com/jp/company/news/2018-05-08/400 Tue, 08 May 2018 00:00:00 -0700 アルデック、Riviera-PRO™に自動UVMレジスタジェネレータ、ユニットリンティング、初期のVHDL 2018拡張機能の3つの機能強化を実施