RTAX/RTSX Netlist Converter

Product Description

RTAX/RTSX EDIF and PDC/PIN Converter combines two functions supporting Aldec RTAX prototyping - it provides EDIFs netlists conversion and PDC/PIN constraints file remapping for two families RTAX-S/SL and RTSX-SU/S, SX-A. RTAX/RTSX EDIF and PDC/PIN Converter performs automatic conversion of the RTAX-S/SL and RTSX-SU/S, SX-A EDIFs netlists to ProASIC3/E EDIF netlist, which means replacement of the PLL and memory primitives has to be done, with consideration of the limitations caused by the differences between RTAX-S/SL, RTSX-SU/S, SX-A and ProASIC3/E technologies.

EDIF and PDC Conversion Flow

RTAX/RTSX EDIF and PDC/PIN Converter also performs automatic conversion of the PDC(RTAX-S/SL) and PIN(RTSX-SU/S, SX-A) constraints file allowing for automatic remapping of the RTAX-S/SL, RTSX-SU/S, SX-A pin locations to ProASIC3/E pin locations according to the interconnections on the Aldec adaptor board.

Those features complement the hardware adaptor enabling a seamless migration from RTAX-S/SL and RTSX-SU/S, SX-A to ProAsic3E technology and facilitate Place & Route process in order to utilize a flash based FPGA for prototyping.

RTAX/RTSX EDIF and PDC/PIN Converter

Benefits:

  • Seamless prototyping with Aldec RTAX-S/SL,RTSX-SU/S, SX-A prototyping boards based on Microsemi SoC ProASIC3/E devices
  • Automatic conversion of the RTAX-S/SL,RTSX-SU/S, SX-A netlist to the ProASIC3/E netlist. No need to perform manual mapping of primitives and memory blocks.
  • Automatic conversion of PDC, PIN constraints file. Together with converted EDIF it deliver easy path for P&R process.
  • Additional library of primitives for memories is available. The library is available as an add-on option to the base configuration

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