Aldec Design and Verification Blog Trending Articles HW/SW Co-Verification Environment for Hybrid Systems Using QEMU 35-years-old, and still on point No Risk No Fun What is Bird’s Eye View ADAS Application and How to Develop This Using Zynq® UltraScale+™ MPSoC FPGA? The Power of PCIe in Performance-based FPGA World HW/SW Co-Simulation for SoC FPGA designs Problems Accessing Registers? – See how UVM RAL can help All Categories Corporate DO-254 Compliance Embedded Solutions Emulation/Acceleration FPGA Design Functional Verification High Performance Computing Requirements Management SoC and ASIC Prototyping SoC Design and Validation Specialized Applications The Power of PCIe in Performance-based FPGA World Understanding High speed serial data transfer In today's world, when the entire computing industry is talking about high-performance and high-speed applications using FPGAs, just what are the factors that can assure such performance and speed?... Tags:Aceleration,ASIC,Co-simulation,Documentation,Embedded,Emulation,FPGA,FPGA Simulation,Hardware,HDL,IP,Prototyping,Simulation,SoC,Validation,Verification,Xilinx Like(2) Comments (0) Read more Do you really need FPGA Design Management? 3 ways Active-HDL™ can help Absolutely, you do. Most of FPGA design today involves FPGAs from multiple vendors, third party IPs and blocks from legacy design. Design reuse also has become a more critical element given the ever decreasing... Tags:FPGA Simulation,Project management Like(1) Comments (0) Read more 2012: Emulation's Big Year And a Look Ahead to 2013 2012 was an exceptional year for Aldec globally. The company exceeded revenue expectations across all product offerings, the most significant changes coming from Emulation. Aldec continued to see double digit growth in our traditional market areas of FPGA and ASIC HDL Verification... Tags:FPGA,FPGA Simulation,Functional Verification,SoC Like(0) Comments (0) Read more
