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Plots: A New Way To Analyze Data

Data analysis is often a very time consuming process for a hardware design or verification engineer. We always end up using the waveform viewer which may not be very efficient in giving us a high-level overview of what we’re looking for. Data that is spread across...

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Understanding the inner workings of UVM
UVM Basics Part 1 of 3

We have all been witnesses to the rapid improvements of the iPhone processor chip every year. With the iPhone 8 featuring the newest A11 Bionic at 10 nm FinFET with 4.3 billion transistors, I can’t personally fathom the amount...

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Key Components of Effective RTL Linting and CDC Verification
Solving your challenges with ALINT-PRO

Automated design rule checking, or linting, has been around the RTL verification for at least a couple decades, still many HDL designers completely ignore this simple yet very powerful bug hunting method. Why would a busy designer need to run this annoying warning generator?...

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FPGA VHDL Verification
How can we do this faster and with better quality - at no extra cost?

This is actually possible – and with an average efficiency improvement of 20 to 50% for medium to high complexity FPGAs. Less for data path oriented designs and more for control or protocol oriented designs. At no extra cost....

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UVM. It’s Organized and Systematic.
Mastering the fundamentals

One of the reasons I like using UVM is its tendency toward an organized structure and uniformity. Some may find it annoying to adhere to such a strict format in UVM, but I think it’s a good way to keep the basics of UVM engrained in your brain....

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A Comprehensive RTL Verification Solution for VHDL
ALINT-PRO™ Design Rule Checking Solution

On Thursday, November 19, I’ll be hosting a webinar to demonstrate Aldec’s RTL Verification Solution for VHDL, ALINT-PRO™ Design Rule Checking Solution.   ALINT-PRO is Aldec’s design verification solution for RTL code...

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Webinars, YouTube, Articles... What’s your preference?
Useful resources to help you get ahead

“USEFUL” is a word you’ll hear a lot over here at Aldec. It’s the number one way we rank our success when developing a new product or feature. “How USEFUL is it?” is the most common phrase we challenge one another...

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How HES™ Technology Solved Problems for These Users
Verification and validation environment for SoC/ASIC designs

Recognizing a problem that engineers are facing and developing a solution has been Aldec’s rather straight-forward mantra for going on thirty years now. Aldec launched its Hardware Emulation Solutions (HES) product in 2003,...

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Visualizing UVM Environments: Debug Features Deliver a Clearer View
Guest Blog from Srinivasan Venkataramanan of CVC

It is an often-quoted statistic that Functional Verification consumes the lion’s share (40-70%) of ASIC and complex FPGA design projects. A less often stated fact, yet no less true, is the majority of verification cycle time is spent...

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Much has changed in the last 30 years
A New Year’s Reflection from Aldec’s founder and CEO

When I first launched Aldec in 1984, home computers hadn’t quite taken off and innovations such as the compact disk and those oversized, power draining cellphones were still struggling to obtain mass acceptance....

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