Name Products Type Action
"glbl.GSR"への階層参照が解決できない    Active-HDL FAQ
# KERNEL: WARNING: NUMERIC_STD."=": metavalue detected, returning FALSE のメッセージを無効にするには?    Riviera-PRO FAQ
#ELBREAD: Warning: Module 'module_name' does not have a `timescale directive がモジュールで指定しているのに表示される    Riviera-PRO FAQ
#KERNEL: WARNING: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es) のワーニングを止めるには?    Riviera-PRO FAQ
.BAKファイルから .BDEファイルをどうやって復元できますか?    Active-HDL FAQ
“signed”、“unsigned”または“integer”タイプを使うと、シミュレーション速度の点で利点がありますか?    Active-HDL FAQ
「TP」ポイントは何のためのものですか?    HES-7 FAQ
05-Running Simulation   
Learn how to run simulation and use waveform viewer in Active-HDL
Active-HDL チュートリアル
Learn how to use HDL debugging tools in Active-HDL
Active-HDL チュートリアル
Learn how to use Design Profiler
Active-HDL チュートリアル
10-Simulink Interface   
Learn how to use Simulink® Interface in Active-HDL
Active-HDL チュートリアル
100% Signal Visibility during Emulation Dynamic Debug with HVD Technology   
Abstract: When it comes to debugging during emulation, engineers are forced to use multiple applications to ensure proper hardware signal data extraction and visualization. Learn from this webinar a leading edge technology that intelligently extracts data from the FPGA emulator to provide 100% signal visibility during emulation. This approach delivers up to 70% bandwidth savings in the critical emulator communication channel. Both dynamic and static probes from emulation can also be visualized in the Riviera-PRO waveform viewer preserving the original signal names and hierarchy paths and providing complete traceability to the design’s RTL source code. Play webinar   
HES-DVM ウェブセミナーの録画
2,400万ASICゲートにアクセスできると計算した根拠は何ですか?    HES-7 FAQ
2つのPCI-Expressを同時に使用できますか?    HES-7 FAQ
3rd パーティーシミュレータでHES を使用することはできますか?    HES-EDU FAQ
7-Series FPGA Chips Programming on the HES7XV690-4000BP Board    HES-7 アプリケーションノート
7シリーズのデバイスのプログラミングにはどのコネクタを使いますか?    HES-7 FAQ
Accelerate DSP Design Development: Tailored Flows   
Learn how to achieve better Digital Signal Processing (DSP) design productivity using Aldec’s integrated design flows, enabled by a number of unique technologies, features, and industry partnerships available within Aldec Riviera-PRO™ design and verification platform. You will learn about the essential and innovative features in the RTL simulation environment that are important to signal processing: Model-based design flow integration, Floating-point aware RTL debugging tools, Dedicated protocol analysis tools, Full support for FPGA silicon vendors. Play webinar   
Active-HDL, Riviera-PRO ウェブセミナーの録画
Accelerate SoC Simulation Time of Newer Generation FPGAs   
Comprehensive verification that can be provided by HDL simulators is good, but not ideal. What is necessary is a faster, safer, and more thorough verification environment that combines the robustness of an HDL simulator with the speed of FPGA prototyping boards. The goal is to put together the power of these two verification methodologies into one platform.
HES-DVM ホワイトペーパー
Accelerate SoC Simulation Time of Newer Generation FPGAs   
Functional verification of a design at the three design stages (RTL, Gate-Level and Post-Route) are essential steps to ensure correct behavior of a design according to requirements, however they are limited by HDL simulator speed. While HDL simulators offer advanced debugging capabilities and provide robust design coverage information, their speed is the primary bottleneck of the design cycle when it comes to verification. This webinar will discuss a faster, safer, and more thorough verification environment that combines the robustness of an HDL simulator with the speed of FPGA prototyping boards. Play webinar   
HES-DVM, HES-7 ウェブセミナーの録画
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