Aldec Design and Verification Blog

Trending Articles
Zynq-based Embedded Development Kit for University Programs
Cost-effective solution for HW/SW development projects

Creativity and innovation, which lead the society to success, rest on the foundational institutions such as schools and universities. They provide fertile soil to seed, grow and flourish enterprises....

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VHDL-2017: Some of My Favorite Things

For the past several years I have had the privilege to chair the IEEE 1076 VHDL working group. In March we handed off the revisions to the VHDL LRM to our technical editor to finalize the document for balloting. As we are waiting for the standards process to finish up, I thought I would share my favorite new additions. Let me start with an executive summary: ...

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The Science of Verification
Boost your Verification Plan with Code Coverage

Science is a product of endless counts of trial and error. Without an error, how can we tell that something is right? This is the main reason why we perform verification....

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Want to be a Verification Engineer? Practice. Practice. Practice.
Simulate UVM & SystemVerilog online for free

HDL design and verification engineers are being absorbed by the job market faster than universities can create them. The desperation of high tech firms is evident in aggressive job posts offering paid relocation, bonuses and other incentives....

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Why Digital Design Students choose Active-HDL™
Mixed-language simulation for VHDL-2008, Verilog and SystemVerilog (Design)

Active-HDL™ STUDENT EDITION is a popular solution for university students looking to enhance their digital design learning experience. A mixed-language simulator that supports VHDL-2008,...

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It’s no accident that Aldec offers the best VHDL-2008 support
Tools, Resources and Training for VHDL Users

Here at the Aldec corporate office, we have a sign that reminds us all of our mission in the field of Technology. It reads, ‘To deliver solutions that provide the highest productivity to value ratio;...

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90’s Kid Active-HDL Celebrates Sweet 16
Serving FPGA Designers as the tool of choice since, like, forever

As the proud Product Manager of Aldec’s  FPGA Design Simulation solution,  I am excited (like it was my first Cranberries concert) to announce that Active-HDL™ is celebrating 16 years since its initial release in 1997....

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Leverage Hardware Acceleration for Faster Simulation
Breaking the Bottleneck of RTL Simulation

Utilizing hardware acceleration in a System-on-Chip verification cycle can speed-up HDL simulation runs from 10-100x, while providing the robust debugging available from an RTL simulator....

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Wait….Did you say HDL Editor?
Productivity Boosting Features

Yes I did, but with no intention to start a holy war on which HDL editor is best. When it comes to HDL editors, each engineer has their own choice and I am not attempting to hurt any madly, deeply felt sentiments. My goal is only to bring the awareness to those using the HDL editor built into Active-HDL™ and...

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