Riviera-PRO Configurations Collapse All Descriptions Expand All Descriptions Show All Editions Features LV[Hide]LVT[Hide]LVT-SV[Hide] Supported StandardsVHDL IEEE 1076 (1987, 1993, 2002 and 2008)ALDEC simulators provide full support of the IEEE 1076-1993 Standard, IEEE 1076™-2002 VHDL standard and majority of just published IEEE 1076™-2008 Standard. More Verilog® HDL IEEE 1364 (1995, 2001 and 2005)ALDEC simulators provide full support of the IEEE 1364-2005 Standard. To enable simulation of a large variety of Verilog designs, both legacy and new, ALDEC simulators can be set to work in Verilog ’95, 2001 and 2005 modes. More SystemVerilog IEEE 1800-2012 (Design)SystemVerilog is a set of extensions to the Verilog HDL that allow higher level of modeling and efficient verification of large digital systems. More SystemC™ 2.3.1 IEEE 1666™/TLM 2.0SystemC is a C library that extends C to enable hardware modeling. Although strictly a C class library, SystemC is sometimes viewed as being a language in its own right More OptionSystemVerilog IEEE 1800™ - 2012 (Verification)Riviera-PRO supports SystemVerilog (IEEE Std. 1800™-2012) in three areas: hardware description extensions, assertions and advanced verification. More --Verification Libraries (OSVVM, UVVM)Verification Libraries (OSVVM, UVVM) More Analog/Mixed Signal (SPICE, Verilog-AMS)Analog/Mixed Signal (SPICE, Verilog-AMS) More RoadmapRoadmapRoadmapUniversal Verification Methodology (UVM)Universal Verification Methodology (UVM) More --Design Entry and Design ManagementHDL and Text EditorThe HDL Editor is a text editor designed for editing an HDL source code. It is tightly integrated with the compiler and simulator to enable debugging capabilities. More Auto-Complete and Code TemplatesThe HDL Editor allows using code autocomplete for all the languages supported by Riviera-PRO. More Automatic Code AnalysisRiviera-PRO’s HDL Editor performs an automatic on-the-fly analysis while source code is being edited: More Design ManagerThe Design Manager is a tool that allows you to view and manage workspaces, attached designs and their resources like HDL source files, waveform files, macros, code coverage and profiler results with a single mouse click. More Customizable GUI PerspectivesWith large number of windows available in Riviera-PRO, keeping all of them open simultaneously is not feasible and frequent reconfiguring of GUI is tedious. More Task ManagementRiviera-PRO enables project task management based on the Tasks window. The window is an easy to use tool which represents current list of tasks assigned within a project. More Macro, Tcl, Perl script supportAldec simulators support several scripting methods varying in the level of abstraction and possible applications. More Debug and AnalysisAdvanced Breakpoint ManagementSimulations can be stopped on a breakpoint. Aldec supports both breakpoints in the source code as well as signal breakpoints. More Interactive Code Execution TracingStepping through source code is one of the most common debugging procedures. Stepping is executing code one line at a time More Accelerated Waveform Viewer (ASDB)The Accelerated Waveform Viewer is a high performance tool for graphical presentation of simulation data stored in a binary simulation database (*.asdb). More Hierarchical References to/from VHDL (Signal Agent)The Signal Agent in VHDL allows monitoring and driving VHDL signals from any VHDL block. More Post Simulation DebugPost Simulation Debug is an advanced feature that allows users to observe the simulation results after the simulation has been finished. More Multiple Waveform WindowsIn large designs where multiple signals must be observed during simulation, keeping them in one waveform window is inconvenient: since all signals cannot fit in one window, frequent scrolling is required to get to the desired waveform data. More Waveform ComparisonThe Compare Waveforms option compares waveforms displayed in the Waveform window with pattern waveforms from a specific waveform file. More Memory ViewerThe Memory Viewer is a debugging tool that has been designed to display memory objects defined in an active design. More Plot WindowPlot window is a debugging tool that visually represents large arrays of data. It support four different plot types and enables HDL design and verification engineers to not only visualize large data sets but also visualize and analyze relations between any objects in their design with no additional programming required. More Image ViewerImage windows is a debugging tool that displays image stored in a memory-like simulation object (Image) or visualizes simulation object values by a color (Color Map). More FSM debugFSM window is debugging tool that allows observing finite state machine operations. This tool generates a transition graph of any simulation object and shows transitions among object states (or signal values). More Integrated Source Level C/SystemC DebuggerRiviera-PRO allows simultaneous and seamless debugging of pure SystemC designs and mixed HDL-SystemC in a single environment. More -Assertions DebuggingDesign and verification engineers who implemented assertions and covers in their project can observe their behavior during regular simulation and debugging in multiple windows. More OptionSynopsys® (formerly SpringSoft) Verdi™ FSDB InterfaceRiviera-PRO output FSDB files that work with Synopsys (formely SpringSoft) Verdi and legacy Debussy debuggers. Riviera-PRO work with Synopsys products in post-processing mode(PSD). More OptionX-TraceX-Trace helps you quickly identify the cause of unexpected values by reporting information on changes from valid to unknown, uninitialized, or user-defined values in the simulated model. More OptionDataflowThe Dataflow window is a powerful tool that allows designers to explore the connectivity of an active design and analyze dataflow among instances, concurrent statements, signals, nets, and registers during simulation. More OptionClasses WindowThe Classes window is a debugging tool that presents SystemVerilog classes in the form of a hierarchical tree view. More --UVM Graph & Toolbox UVM Graph is a tool that presents architecture of the UVM-based testbenches in a graphical format. More --Simulation/VerificationSingle or Mixed LanguageMost ALDEC simulator configurations support mixed (VHDL and Verilog) designs, but single language (VHDL-only or Verilog-only) configurations are also available. More Verilog Programming Language Interface (PLI/VPI)The Verilog PLI (Programming Language Interface) and VPI (Verilog Procedural Interface) provide a standard mechanism to access and modify data in a simulated Verilog model. More VHDL Programming Language Interface (VHPI)The VHPI interface provides a standard means to access data in VHDL models elaborated in Active-HDL and Riviera-PRO. More SystemVerilog IEEE 1800 DPI 2.0DPI, or the Direct Programming Interface, is the next generation interface between SystemVerilog code and foreign C/C++ code. More Value Change Dump (VCD and Extended VCD) SupportThe VCD (Value Change Dump) file format is specified in the IEEE Std. 1364-1995 standard. The VCD file is an ASCII file containing header information, variable definitions, and variable value changes. More Incremental CompilationWith incremental compilation, small change in one of many design sources does not require recompilation of the entire design. Compilers working in incremental mode can ignore not only files that were not changed, but also areas of larger files that were not modified. More Multi-Threaded CompilationCompilers can utilize newer workstations with multiple processors/processor cores to simultaneously translate different parts of the design, significantly reducing compilation times. More Simulation Model ProtectionLibrary protection offers four security levels when compiled models are distributed in the form of library files without releasing their source code. More VHDL IEEE 1076™-2008 EncryptionUsing standard design source encryption is a much easier form of managing IP creation and delivery than any kind of binary file encryption. Riviera-PRO supports standard methodology introduced in IEEE Std. 1076-2008. More Verilog® IEEE 1364™-2005 EncryptionUsing standard design source encryption is a much easier form of managing IP creation and delivery than any kind of binary file encryption. Riviera-PRO supports standard methodology introduced in IEEE Std. 1364-2005. More Intel FPGA Language-Neutral LibrariesThis option enables Aldec customers with VHDL only license to simulate the most recent Intel FPGA Libraries without purchasing a separate Verilog license (which is required as some of the design units written in Verilog/SystemVerilog). More Option (VHDL Only)Microsemi® Language-Neutral LibrariesThis option enables Aldec customers with VHDL-only license to simulate the Microsemi IP without purchasing a separate Verilog license More Option (VHDL Only)Xilinx® SecureIP SupportAldec simulators support the SecureIP methodology of IP delivery implemented in Xilinx tools. More Option (VHDL Only)32/64-Bit Cross-Compatible LibrariesLibrary compatibility across different platforms enables more efficient work of teams working on the same projects, but equipped with different workstations. One set of design libraries can be kept in a convenient location with easy access from all team members. More -64-Bit SimulationThe ability for the simulator to run at 64-bit bus throughput application speeds and utilize extended memory. (Not applicable on Riviera-PRO LV). More -Simulation Performance Optimization (Verilog/SystemVerilog, VHDL)The Verilog RTL & Gate performance optimizer accelerates simulation of all types of Verilog designs, including designs with timing, gate-level designs, and designs with predominantly behavioral code. More -Dynamic Object TracingDynamic Object Tracing refers to advanced capability of Riviera-PRO framework that enables representing SystemVerilog class objects in Waveform Viewer. More Transaction-Level Visual DebuggingTransaction-Level Visual Debugging refers to advanced capability of the Waveform Viewer that enables representing simulation data at a higher level of abstraction. More -OptionProfiler (Performance Metrics)The Profiler identifies design units or code sections that put the greatest strain on the simulator. This information is valuable for optimizing the simulation environment and improving performance. More OptionSFM (Server Farm Manager)Due to the complexity of contemporary designs, there is a need for extensive testing of new products. Server Farm Manager (SFM) shifts the regression paradigm and provides not only simulation technology but also a tool for automatic management of thousands of parallel simulations. More Option 2Option 2Hardware Assisted Verification (Acceleration and Emulation)Acceleration speeds up verification by co-simulating HDL code and portions of the design pushed into hardware (mainly well tested blocks or IP blocks). Emulation allows in-hardware simulation and extensive debugging of large systems that will eventually work on different platform. More Option 3Option 3Option 3Assertions and Coverage ToolsCode Coverage (Statement/Branch, Expression/Condition, Path), Toggle Coverage, Functional Coverage (OSVVM) + New UCIS-compatible Aldec Coverage Database.Code Coverage is a debugging tool that aids the verification process. More OptionPSL IEEE 1850, SystemVerilog IEEE 1800™, OpenVera Assertions and Functional Coverage (Assertion)Specification of properties and their use in assertions and functional coverage is the essential element of designing modern systems and their verification algorithms. More OptionFunctional Coverage (Covergroup)Functional Coverage can provide information about the quality of the design verification process. More --Co-Simulation InterfacesKeysight SystemVue® (formerly Agilent Test and Measurement)Keysight SystemVue co-simulation interface reduces development time and effort by enabling continuous test verification through the system and hardware development process. More MathWorks Simulink®The Simulink Interface simplifies verification of hardware designs by providing robust visualization and analysis toolsets. More MathWorks MATLAB®Aldec simulators integrate The MathWorks' intuitive MATLAB language and a technical computing environment. More OptionAldec QEMU Bridge (Linux Only)Aldec QEMU Bridge it is transaction accurate bridge that allows full SoC co-simulation between the Programmable Logic (PL) system and Processing System (PS) More OptionDesign Rule CheckingALINT-PRO with Basic Rule LibraryAldec® ALINT-PRO™ analyzes VHDL, Verilog and Mixed Language HDL code during compilation, prior to simulated or synthesized. More Option 4DO-254 Verilog or VHDL Rule LibraryALINT supports new sets of rules that facilitate compliance with DO-254. More Option 4Option 4Option 4STARC Verilog or VHDL Rule LibrarySTARC® based programmable design and coding guideline checker of complex system-on-chip designs. More Option 4Option 4Option 4RMM (VHDL and Verilog)Reuse Methodology Manual (RMM) design rule library is based on the industry-proven manual from Synopsys Inc. and Mentor Graphics Corp. which defines the methodology for effective design reuse and verification. More Option 4Option 4Option 4LicensingFloating LicenseThe network floating configuration (multiple users) is based on a license started on a remote machine (license server) running on the Windows or Linux platform. More One Year Time Based LicenseOne Year Time Based License (TBL) grants a designer a license to use the product for a period of one year. A 1 year support contract is included with the purchase of TBL license. More Perpetual LicenseA perpetual license is a license with no expiration date. A 1 year support contract is included with the purchase of perpetual license. More Supported PlatformsLinux® (32/64-Bit)Linux x86/x86_64 support. More Windows® 10/8.1/8/7/2012/2008/2003 - (32/64-Bit)Builds are tested on all the latest platforms to ensure correct operation on users' workstations. More Option 2 - Server Farm Manager is a separate Aldec productOption 3 - Hardware Assisted Verification is a separate Aldec product - HESOption 4 - ALINT™ is a separate Aldec product, STARC, DO-254 and RMM packages are sold separatelyRoadmap - Sign In Username: Password: Forgot your password? Sign In Close Ask Us a Question x Ask Us a Question x Name: Phone: Email: Question: Security code: Incorrect data entered. Thank you! Your question has been submitted. Please allow 1-3 business days for someone to respond to your question. Internal error occurred. Your question was not submitted. Please contact us using Feedback form.