SystemVerilog IEEE 1800™ - 2012 (Verification)

Category : Supported Standards

SystemVerilog IEEE 1800 - 2012 (Verification) - Partial Support

Riviera-PRO supports SystemVerilog (IEEE Std. 1800™-2012) in three areas: hardware description extensions, assertions and advanced verification. The latter, known as the Verification portion of the standard includes constructs such as classes, random constraints, coverage groups, design assertions, etc. to enable self-checking and coverage driven testbench design.
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