Verification Libraries (OSVVM, UVVM, cocotb)

Category : Supported Standards

Open Source VHDL Verification Methodology™ (OSVVM™) provides a methodology and library to simplify the entire verification effort. OSVVM supports the same capabilities that other verification languages support – from transaction level modeling, to functional coverage and randomized test generation, to data structures, and to basic utilities.


UVVM VVC Framework provides a FPGA verification environment with better overview, readability and maintainability. It also increases the probability of detecting corner case design bugs. The tool supports constrained random stimuli, coverage verification and efficient verification reuse.


cocotb is a COroutine based COsimulation TestBench environment for verifying VHDL and SystemVerilog RTL using Python. cocotb is completely free, open source (under the BSD License) and hosted on GitHub. cocotb requires a simulator to simulate the HDL design and has been used with a variety of simulators on Linux, Windows and macOS.

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