Aldec Design and Verification Blog Trending Articles Scalable Cloud-based CI/CD HDL Verification Environment Navigating VUnit: A Practical Guide to Modifying Testing Approaches Speeding Up Simulation with VUnit for Parallel Testing Introduction to VUnit FPGA Design Verification in a Nutshell Versal ACAP Simulation Challenges Real-time SDR system with TySOM All Categories Corporate DO-254 Compliance Embedded Solutions Emulation/Acceleration FPGA Design Functional Verification High Performance Computing Requirements Management SoC and ASIC Prototyping SoC Design and Validation Specialized Applications The Convergence of Emulation and Prototyping During the development of a system on chip (SoC), hardware emulation and FPGA prototyping play distinct and essential roles. ● Emulation is used to verify that a design meets its functional requirements, where the verification is performed by emulating the hardware and simulating (using a testbench) the environment in which it must perform.... Tags:ARM,ASIC,Emulation,FPGA,SoC,Validation,Verification Like(3) Comments (0) Read more Connecting Emulated Design to External PCI Express Device These days verification teams no longer question whether hardware assisted verification should be used in their projects. Rather, they ask at which stage they should start using it. Contemporary System-on-Chip (SoC) designs are already sufficiently complex to make HDL simulation... Tags:ARM,ASIC,Emulation,FPGA,SoC,Validation,Verification Like(2) Comments (0) Read more ARM-based SoC Co-Emulation using Zynq Boards Ready-to-use Co-Emulation Platform Have you ever worked on a group project where you had to combine your work with that of a colleague of a different engineering discipline but the absence of an efficient means of doing so affected the project’s overall outcome?... Tags:ARM,ASIC,Emulation,FPGA,SoC,Validation,Verification,Zynq Like(1) Comments (0) Read more The Power of PCIe in Performance-based FPGA World Understanding High speed serial data transfer In today's world, when the entire computing industry is talking about high-performance and high-speed applications using FPGAs, just what are the factors that can assure such performance and speed?... Tags:Aceleration,ASIC,Co-simulation,Documentation,Embedded,Emulation,FPGA,FPGA Simulation,Hardware,HDL,IP,Prototyping,Simulation,SoC,Validation,Verification,Xilinx Like(3) Comments (0) Read more The Race to Zero Latency for High Frequency Trading The High-Frequency Trading (HFT) industry has received a lot of attention during the last few years. HFT is all about speed and minimizing latency: the faster you can run trading strategies and algorithms for analyzing minute price changes... Tags:Aceleration,Coverage,Verification,Verilog,VHDL Like(2) Comments (0) Read more Emulation in FPGA For many years, emulators were available only to verification teams working on the largest projects in companies with deep enough pockets. Due to size rather than capabilities they were called “Big Box” emulators and typically were used in order to recover... Tags:ARM,Emulation,Prototyping,Verification,Xilinx Like(1) Comments (0) Read more Accelerating Simulation of Vivado Designs with HES Improve verification speedup with Aldec’s HES-DVM FPGA Design Verification Challenge The FPGA design and verification “ecosystem” changes rapidly to keep pace with the fast growing size of FPGA devices. The largest Xilinx Virtex UltraSCALE chips provide 4.4 Million logic cells... Tags:Aceleration,Co-simulation,FPGA,Simulation,Verification,Xilinx Like(1) Comments (0) Read more How can Verification IPs Help the SoC Testing Process? How to use VIPs In Practice Let’s assume that we are designing a new system on chip (SoC) which contains a processor and memory controller, as well as analog and digital peripherals like Ethernet, USB, 1-Wire and JTAG controllers.... Tags:Emulation,Hardware,UVM,Verification Like(2) Comments (0) Read more Transitioning to Advanced Verification Techniques for FPGAs – Catch-22? A Guest Blog by TVS Founder and CEO, Dr. Mike Bartley Many FPGA designers find themselves in a catch-22: they recognise that their designs are becoming too complex for their current verification strategies BUT adopting advanced verification techniques (such as the Universal Verification Methodology – UVM) is... Tags:FPGA,Randomization,Verification,Coverage,Digital,IP,Simulation,Verilog,VHDL Like(2) Comments (0) Read more How HES™ Technology Solved Problems for These Users Verification and validation environment for SoC/ASIC designs Recognizing a problem that engineers are facing and developing a solution has been Aldec’s rather straight-forward mantra for going on thirty years now. Aldec launched its Hardware Emulation Solutions (HES) product in 2003,... Tags:Aceleration,Debugging,Embedded,Emulation,UVM,Verification Like(1) Comments (0) Read more
