Advancing VHDL’s Verification Capabilities with VHDL-2019 Protected Types March 29 Aldec Suspends all EDA Sales and Distribution Transactions in Russia March 14 Industry’s First use of TLM for the At-Speed Verification of a PCIe-Based Avionics Design Requiring DO-254 Compliance January 13 Productivity Through Methodology: Aldec Adds UVM Generator to Riviera-PRO™ Plus Updates Its OSVVM and UVVM Libraries November 16 New HES Board is Ideal for Prototyping and Emulating Medium to Large ASIC & SoC Designs July 19 View all news
FPGA Design/Verification Best-Practices for Quality and EfficiencyPart 4: Code, Functional and Specification Coverage (US) May 19 (Webinar, Online) FPGA Design/Verification Best-Practices for Quality and EfficiencyPart 4: Code, Functional and Specification Coverage (EU) May 19 (Webinar, Online) Better FPGA Verification with VHDLPart 1: OSVVM - Leading Edge Verification for the VHDL Community (EU) May 26 (Webinar, Online) Better FPGA Verification with VHDLPart 1: OSVVM - Leading Edge Verification for the VHDL Community (US) May 26 (Webinar, Online) Better FPGA Verification with VHDLPart 2: Faster than "Lite" Verification Component Development with OSVVM (EU) Jun 09 (Webinar, Online) View all events
FPGA Design/Verification Best-Practices for Quality and EfficiencyPart 4: Code, Functional and Specification Coverage FPGA Design/Verification Best-Practices for Quality and EfficiencyPart 3: Randomization – The Why, When, What & How FPGA Design/Verification Best-Practices for Quality and Efficiency Part 2: FPGA Verification Architecture Optimization with UVVM FPGA Design/Verification Best-Practices for Quality and Efficiency Part 1: FPGA Design Architecture Optimization Running CDC Analysis with Xilinx Parameterized Macros View all webinars
