HES Proto-AXI Host Interface

Aldec HES™ Proto-AXI is a host interface module that provides:

  • A standardized local bus of AMBA AXI to connect with the user’s design
  • Simple C API that is used to implement various types of software driven testbenches or integrate with other testbench tools and environments


Aldec provides two types of Proto-AXI interfaces:

  • PC Host type is a high speed implementation of the PCIe to AXI bridge capable of transmitting data between the host and the FPGA at 2GB/s rate while hiding implementation complexity and ensuring the shortest engineers’ ramp-up cycle.
  • Embedded type is a low latency implementation of the embedded host interface. In this case the testbench runs in an embedded system (Linux) inside the Xilinx Zynq MPSoC device that is placed along with the large UltraScale FPGA on the same HES board. The Embedded type benefits from the powerful ARM Cortex-A9 architecture of Zynq devices and enables building very compact prototype testbenches or customer’s demo platforms.


They are compatible with each other at the hardware level (the same Proto-AXI IP) and software level (the same software API).




Max. Throughput Min. Round-trip message latency
  Proto-AXI PC Host 2000 MB/s 33 us
  Proto-AXI Embedded 1245 MB/s 15 us

 Benchmarking data for HES-US-440 board

  • Max throughout measured using burst transfers
  • Min Round-trip message latency measured using 32-bit datagrams


Both types also provide an easy access to all kinds of on-board memories without the need of configuring custom memory controllers. These memories are accessible at pre-configured address ranges of the AMBA AXI subsystem. Proto-AXI allows connecting multiple user design modules that can be both Master and Slave memory mapped AXI devices. Moreover, all these devices can transfer data with one another thanks to the AXI interconnect contained in Proto-AXI IP. The memory map of Proto-AXI can be customized thanks to configurable memory remappers included in the Proto-AXI IP. There are also GPI/GPIO lanes in the Proto-AXI IP used to realize non-standard interfaces or to transfer status or configuration data directly without using AXI protocol. An example of the Proto-AXI IP configuration on the HES-US-440 board is shown in the following block diagram.




Key Features & Benefits

  • Easy to use host interface to implement various testbenches
  • Based on widely adopted AMBA AXI standard
  • Reduces host interface implementation overhead
  • Provides bridges to all on-board memories
  • AXI Interconnect enables connecting multiple DUT modules
  • High throughput PC-Host interface based on PCI Express
  • Low latency Embedded host interface
  • Allows building software driven testbenches
  • Embedded version enables one-board prototype & testbench solution utilizing ARM Cortex processor



  • HES Proto-AXI IP module
  • HES Proto-AXI C API
  • HES Proto-AXI System Verilog simulation model with DPI-C bridge to Proto-AXI API
  • Host PC bridge and Embedded Zynq high speed infrastructure
  • Embedded Linux port for Zynq containing Proto-AXI API
  • PCIe Driver for Host PC Linux & MS Windows
  • Examples & User Guide
Ask Us a Question
Ask Us a Question
Captcha ImageReload Captcha
Incorrect data entered.
Thank you! Your question has been submitted. Please allow 1-3 business days for someone to respond to your question.
Internal error occurred. Your question was not submitted. Please contact us using Feedback form.
We use cookies to ensure we give you the best user experience and to provide you with content we believe will be of relevance to you. If you continue to use our site, you consent to our use of cookies. A detailed overview on the use of cookies and other website information is located in our Privacy Policy.