Today’s SoC FPGAs present new verification challenges for system, software and hardware engineers. Common issues related to HW/SW integration continue to increase, and yet they are only typically found in the testbed with the SoC FPGA running. Finding the issues in the testbed is often too late and can cause project delays.

Aldec provides a HW/SW co-simulation interface between Riviera-PRO™ and QEMU (open-source processor emulator). System integration and co-simulation of HDL code with software applications/drivers executing in QEMU is now simplified with the addition of the Aldec QEMU Bridge. The QEMU Bridge connects Riviera-PRO and QEMU, and converts SystemC TLM transactions to AXI and vice versa providing a fast interface for co-simulation.


Figure 1: HW/SW Co-Simulation Environment with Riviera-PRO and QEMU



AXI BFM with Transaction Recorder

The AXI Bus Functional Models (BFMs) developed by Aldec for RTL simulation of AXI-based designs is available in Riviera-PRO. The BFMs are delivered as encrypted Verilog and System Verilog modules. User test bench can test the BFMs via Verilog or System Verilog tasks API provided by Aldec. The following BFMs are supported by the Aldec AXI BFM:

  • AXI 3 Master
  • AXI 3 Slave
  • AXI 4 Master
  • AXI 4 Slave
  • AXI 4 Lite Master
  • AXI 4 Lite Slave
  • AXI 4 Stream Master
  • AXI 4 Stream Slave


Each BFM enables users to turn on built-in AXI transaction recorder for logging AXI transactions into ASDB (Aldec Simulation Database) format. For more information about using transactions in Riviera-PRO, refer to documentation Riviera-PRO Transactions. The process of AXI injection into design includes:

  • Design Stage
    • Distributed with pre-compiled libraries
    • Instantiation in HDL part of the project
  • Compilation and Configuration Stage
    • Configuration set by parameters
    • Turn on built-in AXI transaction recorder
  • Simulation Stage
    • Automatic connection with QEMU Bridge process



Figure 2: AXI Transactions in Riviera-PRO

QEMU Bridge

Developed by Aldec based on SystemC Transaction Level Modeling (TLM), it is transaction accurate bridge that allows full SoC co-simulation between the Programmable Logic (PL) system and Processing System (PS). The communication is automatically handled by this bridge, and there is no need for extra interaction from verification engineer side.

Hardware engineers (using Riviera-PRO) can set break points in the HDL, examine data flow, and even analyze the code coverage and paths that are exercised by the software application running in QEMU. Software engineers (using QEMU) can use GNU Debugger (GDB) to instrument both the kernel and the driver to step through the code using breakpoints.


QEMU for Xilinx SoC FPGAs

Xilinx® provides QEMU tree for Microblaze™, Zynq™ and Zynq UltraScale+. The QEMU tree must be downloaded and installed by the user. Xilinx recommends that users download the QEMU tree provided at https://github.com/Xilinx/qemu.

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