Play WebinarTitle: FPGA Verification with VHDL and UVVM Part 2: Harnessing the power of VVCs and BFMs Description: Riviera-PRO includes a pre-compiled version of the latest UVVM, providing users with direct access to a robust verification methodology for VHDL designs. Along with this, Riviera-PRO users gain access to a comprehensive set of free and high-quality BFMs and VVCs (VHDL Verification Components) for immediate use in their testbenches. This simplifies and accelerates the verification process, offering a strong starting point for FPGA or ASIC verification projects. With ready-to-use BFMs and VVCs, users can apply them directly for standard interface tasks — a true plug-and-play experience. Within minutes of downloading, you could be executing commands like axistream_transmit(), axi_write(), uart_expect(), or ethernet_receive(). For more advanced interface management, such as introducing randomized behavior like toggling the AXI-stream valid signal, configuration records can be customized. Many UVVM users leverage these capabilities to uncover hidden design bugs early in the development cycle. In this webinar, we will demonstrate how to effectively use UVVM BFMs and VVCs, offering insights into their differences and best use cases. Whether you're tackling straightforward verification tasks or working with complex DUTs and stringent quality requirements, we will cover practical tips and strategies to optimize your verification efforts.Signing up for an account is easy. With an Aldec account you'll have easy, one-click access to event registration, support, product downloads, evaluation licenses, recorded webinars, white papers, application notes and other resources. Simply provide your corporate e-mail address below - all account requests are verified and confirmed within 48 hours. If you already have an Aldec account, please Sign In below to download the file. Register Sign In
