Aldec Springs Into Action

A look back at a busy industry show season

Henry Chan, Applications Engineer
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It’s been a busy season for Aldec. The weather has warmed here in the desert and as the trees and greenery enliven in spring, Aldec has also been bursting with activity. From DVCon to the International Symposium on FPGAs in the US to Embedded World and CTIC in Europe, there have been some exciting developments from Aldec in verification, embedded systems, and DO-254.

 

These major events and conferences have been a great time to provide some updates on the latest Aldec endeavors and to provide an in-person look at the capability of our tools.

                      

The DVCon U.S. Conference and Exhibition held in San Jose, California, holds a special place in my heart because it was the first industry conference I attended after starting my career in EDA. Every year I enjoy returning in order to see the latest verification advancements and to speak with those who are hard at work trying to improve verification efforts. Portable stimulus was a hot topic and it seemed like emulation was growing in popularity. This year we brought our Hardware Emulation Solutions (HES™) so that people could get an in-person look at our hardware. We showed off the speed benefits of emulation over traditional simulation by hooking up a UVM testbench to an in-house network-on-chip design running in our FPGA boards. As design sizes increase, I think emulation will become a more widely adopted solution to the simulation bottleneck.

 

At isFPGA2017, it was an exciting experience to educate attendees on the benefits of using FPGAs in genomic research and big data analysis in the biomedical industry. We showed how ReneLife, a company which spawned out of the Indian Institute of Science, was able to accelerate their genome alignment algorithm using our HES FPGA HPC platform to speeds 10x faster than when using conventional GPU acceleration methods. Our motion detection demo also attracted some eyes as we accelerated an object-detection image processing algorithm using two Xilinx® Virtex®-7 FPGAs on our HES7-4000 FPGA board. Overall, FPGAs are starting to become a likely candidate for the solution to the end of Moore’s law. When you can’t depend on shrinking process nodes for performance gains, parallel computing using FPGAs starts to look very enticing.

 

Our exhibit at Embedded World displayed a new bridge between our Riviera-PRO™ simulator and QEMU. The idea is to have your drivers and user application running in a QEMU environment on top of an ARM® processor model. This ARM processor model can be an analog for the ARM processor in a Xilinx Zynq chip you are targeting. While the software is running in QEMU, your hardware design is running in Riviera-PRO as a simulation. QEMU is connected to Riviera-PRO and your software is used as the stimulus for the simulation. This strategy cuts down on verification time because you don’t need to develop some complicated testbench which may or may not cover your entire design. In this situation, you have a fairly high level of confidence that your design is functionally correct if you can run your production software on it.

 

We also had the opportunity at Embedded World to show off some of our more interesting TySOM™ demos related to autonomous driver assistance systems (ADAS). As the idea of autonomous cars gains traction (pun intended), these systems (which aid the driver with lane departure warnings, blindspot detection, and driver monitoring) become increasingly more desirable. What we’ve shown is that you can provide all these great features in your vehicle using Xilinx Zynq SoC FPGAs in an incredibly small form factor with our TySOM platform. Our multicamera 360-degree surround view and face detection reference designs use the Zynq programmable logic for computationally intensive image processing while the processing system potentially handles any decisions based on the processed images.

 

The Certification Together International Conference (CTIC) for the Aerospace industry was held towards the end of March in France to discuss system, software, and hardware certification challenges. Naturally, our DO-254 team visited the conference to share their knowledge and experience with DO-254. The team presented their “Physical Testing of SoC FPGAs: A HW/SW Co-Verification Approach” talk to provide some insight into new techniques for verifying complex SoC FPGA designs. Stakes are high in the Aerospace industry due to safety-critical requirements and Aldec has the expertise and tools to help achieve DO-254 compliance.

 

That’s just a snapshot of what we’ve been up to. Are you planning to attend any industry events this year? Please feel stop by and visit us at upcoming events like Matlab Expo in Paris, the Trading Show in Chicago, DAC in Austin, and others to learn more about our latest innovations. Hope to see you out there on the show floor.

 

To learn more, we invite you to contact us directly at +1-702-990-4400 or sales@aldec.com.

 

 

As an Aldec Applications Engineer, Henry has intimate knowledge of the inner workings behind the latest verification tools, languages, and methodologies. He has a wide breadth of experience across various areas including simulation, emulation, and embedded systems. Henry received his B.S. in Computer Engineering from the University of Nevada, Las Vegas.

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