Bridging Simulation and Hardware

Whether developing FPGAs, ASICs, or AI-enabled embedded systems, verification remains one of the most challenging and time-consuming phases of the development process. Hardware-in-the-Loop (HIL) testing is transforming this process. By merging simulation and real hardware into a single real-time verification environment, HIL enables faster, safer, and more accurate validation — long before physical prototypes are ready.

What Is Hardware-in-the-Loop (HIL)?

Hardware-in-the-Loop (HIL) is a real-time verification methodology that integrates simulated system models with physical hardware components. It allows engineers to replace certain hardware blocks with high-fidelity software models that behave identically to their real counterparts.

This enables engineers to:

• Perform early validation of hardware and firmware functionality.
• Test fault scenarios safely and repeatably.
• Improve time-to-market with faster iteration cycles.

However, HIL can be complex to implement due to synchronization between software models, real-time interfaces, and hardware execution. Aldec addresses this with a fully automated HIL environment built around its flagship verification tools.

The Aldec HIL Setup: Simulation Meets Hardware

Aldec’s Hardware-in-the-Loop (HIL) verification solution brings simulation and hardware into perfect alignment. It combines Riviera-PRO, VUnit, and the TySOM Zynq MPSoC board into one intelligent ecosystem designed for FPGA and SoC verification, AI prototyping, and real-time hardware validation.

1. VUnit – Automated Test Orchestration

VUnit serves as the automation backbone of the HIL setup. Using Python scripting, it orchestrates simulations, runs regression tests, generates configuration data, and validates results — all without manual intervention. Engineers can execute multiple test suites in parallel and automatically verify encryption, communication, or AI algorithms in hardware.

2. Riviera-PRO – Advanced Simulation and Debugging

Riviera-PRO, Aldec’s high-performance HDL simulation platform, is used to model, simulate, and debug digital designs. It provides advanced waveform visualization, test planning, and code coverage analysis. Engineers can view real-time signal activity, use bookmarks and cursors, and generate automated coverage reports to track test completeness.

Riviera-PRO’s Python integration with VUnit ensures that the simulation results and hardware data are synchronized and verified in one continuous flow.

3. TySOM Zynq MPSoC – Real Hardware Execution

The TySOM board acts as the hardware testbed. Built on the Zynq UltraScale+ MPSoC, it combines programmable logic and embedded processing in a single board. In Aldec’s HIL setup, the programmable logic is used to execute design modules such as cryptographic cores, data interfaces, or AI accelerators in real time.

This allows engineers to validate hardware blocks under realistic conditions while maintaining control and observability through simulation.

4. Aldec USB Bridge IP – Seamless Host-FPGA Communication

A crucial part of Aldec’s setup is the Aldec USB Bridge IP, implemented directly in the FPGA fabric. It enables high-speed communication between the simulation host and the TySOM hardware. The bridge supports bi-directional data exchange between the Python-based VUnit environment and FPGA hardware, ensuring low-latency synchronization between simulation and real-world operation.

Why It Matters

This integrated setup allows engineers to:

• Verify HDL modules and system-level interactions in real hardware.
• Automate testing and debugging with minimal setup time.
• Accelerate FPGA verification for AI, automotive, and embedded applications.
• Gain full traceability between simulated signals and live hardware behavior.

The figure above illustrates Aldec’s Hardware-in-the-Loop (HIL) verification setup for AES encryption and decryption. On the Host PC, tools such as VUnit, Python automation, and Riviera-PRO manage test orchestration, simulation, and result validation. The process begins with a pre-configured script that generates plaintext and encryption keys in hexadecimal format. During simulation, the testbench (TB) performs AES encryption, verifies the output, and exports the encrypted data and key to a text file.

This data is transferred via a USB interface through an FMC Daughter Board to the TySOM FPGA board, where Aldec’s USB Bridge IP manages high-speed communication with the programmable logic. The FPGA then executes AES decryption in real time using the AXI Stream interface. The decrypted text is sent back to the host system, where the post-check function compares it against the original plaintext to confirm end-to-end correctness.

This setup demonstrates a complete closed-loop verification process, combining the precision of simulation-based verification with the performance of FPGA hardware execution. It highlights how Aldec’s integrated HIL framework enables real-time co-simulation, automated data exchange, and comprehensive validation for complex FPGA and AI hardware designs.

Conclusion

Aldec’s Hardware-in-the-Loop verification framework redefines the relationship between simulation and hardware. By integrating Riviera-PRO, VUnit, and the TySOM FPGA platform, it delivers a unified, automated, and intelligent environment for verifying FPGA, SoC, and AI-based designs in real time.

See the techniques, live demonstrations, and HIL in action. Watch the full webinar to explore these insights further. For additional resources and a free trial of ALINT-PRO, visit www.aldec.com/products or contact sales@aldec.com for more information.

Watch the Webinar: Bridging Simulation and Hardware: Hardware-in-the-Loop in Action