Aldec Design and Verification Blog Trending Articles 35-years-old, and still on point No Risk No Fun What is Bird’s Eye View ADAS Application and How to Develop This Using Zynq® UltraScale+™ MPSoC FPGA? HW/SW Co-Simulation for SoC FPGA designs The Power of PCIe in Performance-based FPGA World Problems Accessing Registers? – See how UVM RAL can help The Race to Zero Latency for High Frequency Trading All Categories Corporate DO-254 Compliance Embedded Solutions Emulation/Acceleration FPGA Design Functional Verification High Performance Computing Requirements Management SoC and ASIC Prototyping SoC Design and Validation Specialized Applications Verification Effectiveness with Riviera-PRO: SystemVerilog Randomized Layered Testbench Understanding SystemVerilog Layered Testbench In this blog, I will discuss randomized layered testbenches used in SystemVerilog. We need to understand why we need it,... Tags:Riviera-PRO,ASIC,Assertions,Co-simulation,Coverage,Debugging,Design,Documentation,FPGA,HDL,IEEE,OS-VVM,Randomization,Simulation,standards,SystemVerilog,UVM,Verification,Verilog Like(3) Comments (0) Read more Trace Your Assertions When I enter the word “assertions” into a search engine I get lots of results, including articles, books, courses, and tools. Nothing unusual there, as assertions have been present in the EDA industry for many years. They considerably increase... Tags:Assertions,Debugging,Simulation,SystemVerilog Like(1) Comments (0) Read more 90’s Kid Active-HDL Celebrates Sweet 16 Serving FPGA Designers as the tool of choice since, like, forever As the proud Product Manager of Aldec’s FPGA Design Simulation solution, I am excited (like it was my first Cranberries concert) to announce that Active-HDL™ is celebrating 16 years since its initial release in 1997.... Tags:Assertions,Co-simulation,Coverage,Debugging,Design,Digital,Documentation,FPGA,HDL,IEEE,Matlab,OS-VVM,Simulation,standards,university,Verification,Verilog,VHDL,Xilinx Like(1) Comments (2) Read more
