Aldec Design and Verification Blog Trending Articles Performing cross spectrum video processing on a TySOM-3 board How does the Mars Perseverance rover benefit from FPGAs as the main processing units? SynthHESer - Aldec’s New Synthesis Tool Linting RISC-V designs with ALINT-PRO Enabling TySOM Zynq-based Embedded Development Board for AWS IoT Greengrass Connecting Emulated Design to External PCI Express Device Is your Verification plan pulling you in multiple directions? Try FSM Coverage All Categories Corporate DO-254 Compliance Embedded Solutions Emulation/Acceleration FPGA Design Functional Verification High Performance Computing Requirements Management SoC and ASIC Prototyping SoC Design and Validation Specialized Applications Verification Effectiveness with Riviera-PRO: SystemVerilog Randomized Layered Testbench Understanding SystemVerilog Layered Testbench In this blog, I will discuss randomized layered testbenches used in SystemVerilog. We need to understand why we need it,... Tags:Riviera-PRO,ASIC,Assertions,Co-simulation,Coverage,Debugging,Design,Documentation,FPGA,HDL,IEEE,OS-VVM,Randomization,Simulation,standards,SystemVerilog,UVM,Verification,Verilog Like(3) Comments (0) Read more It’s no accident that Aldec offers the best VHDL-2008 support Tools, Resources and Training for VHDL Users Here at the Aldec corporate office, we have a sign that reminds us all of our mission in the field of Technology. It reads, ‘To deliver solutions that provide the highest productivity to value ratio;... Tags:HDL,IEEE,Simulation,standards,Verification,VHDL Like(2) Comments (0) Read more 90’s Kid Active-HDL Celebrates Sweet 16 Serving FPGA Designers as the tool of choice since, like, forever As the proud Product Manager of Aldec’s FPGA Design Simulation solution, I am excited (like it was my first Cranberries concert) to announce that Active-HDL™ is celebrating 16 years since its initial release in 1997.... Tags:Assertions,Co-simulation,Coverage,Debugging,Design,Digital,Documentation,FPGA,HDL,IEEE,Matlab,OS-VVM,Simulation,standards,university,Verification,Verilog,VHDL,Xilinx Like(1) Comments (2) Read more
