Event Details View All Recorded Events Date Event Type 場所 Action Jan 22, 2026 Best-Practices for Mixed-Language FPGA Design and Verification (EU) Time: 11:00 AM - 12:00 PM (CET) Webinar Overview As modern FPGA projects continue to integrate IP developed in multiple HDLs, effective mixed-language design and verification has become essential for maintaining productivity, reuse, and verification completeness. While mixed-language flows are widely supported, both implementation tools and simulators can impose restrictions that must be clearly understood to avoid costly surprises late in the design cycle. In this webinar, we will review the practical rules, limitations, and recommended methodologies for building and verifying mixed-language designs using VHDL and Verilog. We will explore real-world demo designs that implement FIFO functionality in both languages, paired with directed and randomized testbenches written in the opposite HDL. Through these examples, we will compare various mixed-language verification strategies, evaluate their efficiency, and highlight best practices for building robust, maintainable test environments. Agenda: The role of mixed-language development in modern FPGA designs Challenges and motivations for combining VHDL and Verilog Overview of tools and simulation environments Mixed-Language Design Rules and Implementation Restrictions Avoiding common pitfalls during synthesis and implementation with ALINT-PRO Mixed-Language Verification Strategies Demonstration: FIFO Design Examples Example 1: FIFO in Verilog with VHDL testbench Example 2: FIFO in VHDL with a directed Verilog testbench Example 3: FIFO in VHDL with a randomized Verilog testbench Efficiency Comparison and Best-Practice Recommendations Q&A Presenter BIO Alex Gnusin, Aldec’s ALINT-PRO Product ManagerAlex accumulated 27 years of hands-on experience in various aspects of ASIC and FPGA design and verification. As a verification prime for a multi-million gates project in companies such as IBM, Nortel, Ericsson and Synopsys Inc, he combined various verification methods such as static linting, formal property checking, dynamic simulation and hardware-assisted acceleration to efficiently achieve design verification goals. He received his M.S. in Electronics from Technion, Israel Institute of Technology. ウェブセミナー Online More Info
