Aldec Design and Verification Blog Trending Articles Bridging Simulation and Hardware Advanced Static Linting for FPGA Performance Optimization Scalable Cloud-based CI/CD HDL Verification Environment Navigating VUnit: A Practical Guide to Modifying Testing Approaches Speeding Up Simulation with VUnit for Parallel Testing Introduction to VUnit FPGA Design Verification in a Nutshell All Categories Corporate DO-254 Compliance Embedded Solutions Emulation/Acceleration FPGA Design Functional Verification High Performance Computing Requirements Management SoC and ASIC Prototyping SoC Design and Validation Specialized Applications SynthHESer - Aldec’s New Synthesis Tool In the early days of digital design, all circuits were designed manually. You would draw K-map, optimize the logic and draw the schematics. If you remember, we all did many logic optimization exercises back in college.... Tags:Xilinx,Aceleration,Design,Embedded,Emulation,HDL,SystemVerilog,Verilog Like(2) Comments (2) Read more Integrating SystemVerilog and SCE-MI for Faster Emulation Speed Developing your own Emulation API In the last SCE-MI article, we discussed how SCE-MI macro-based infrastructures can speedup SoC design verification time. In SCE-MI 2.1, Accelera introduced a ‘function-based’ infrastructure... Tags:Emulation,SoC,SystemC,SystemVerilog,Verification Like(3) Comments (0) Read more Increased Debug Capability with Hardware Emulation Hardware emulators enable a rich environment for debugging complex SoC esigns by providing advantages from both software and hardware. Typically, in software simulation designers can set breakpoints, observe waveforms, and trace signals as they progress through a test bench, but are constrained by the... Tags:HES,Aceleration,Emulation,ASIC,SoC,Debugging,Verification,Simulation,SystemVerilog Like(1) Comments (0) Read more
