Integrating SystemVerilog and SCE-MI for Faster Emulation Speed

Developing your own Emulation API

Bill Jason P. Tomas, Product Engineer, Hardware Division
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In the last SCE-MI article, we discussed how SCE-MI macro-based infrastructures can speedup SoC design verification time. In SCE-MI 2.1, Accelera introduced a ‘function-based’ infrastructure which is based on SystemVerilog DPI functionality. The SystemVerilog DPI is an interface which can be used to connect SystemVerilog files with foreign languages (C, C++, SystemC, etc). 

 

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This new interface provides users with multiple benefits when dealing with an emulation environment including:

 

  • No Pre-defined Emulation API

In macro-based SCE-MI, the user is held to a pre-defined C/C++ API which can be used to interface with synthesizable macros implemented in the hardware emulator.  Such components included SceMi initialization and shutdown, messing input/output port proxy binding, error handling, etc.  SystemVerilog DPI uses simple function calls as a mechanism for inter-language communication. This enables the user more flexibility to create their own API, defining the functions in one language and calling them in another.

 

  • The Function Call is the Transaction

During communication between high-level testbench and signal-level DUT, the functional call itself is the transaction, along with the function call arguments (inputs and outputs) being the transactions data members. This avoids having to use slices and bit fields of a single large vector which is used in macro-based SCE-MI.  Although the SystemVerilog LRM allows for a multiple range of data types to be passed for function arguments, SCE-MI restricts to a subset containing bit vectors and integers.

 

  • Mid-level of Abstraction

The SystemVerilog SCE-MI approach is closer to the TLM compared to macro-based which is closer to the signal-level. This ‘mid-level’ of abstraction has benefits from both low and high levels of abstraction. Function-based SCE-MI has a low enough abstraction level for synthesizability and the ability to use with legacy ANSI C code. It also has a high enough abstraction for building user-defined transactor applications, building simulation oriented verification IP, providing a deterministic programming interface, and providing a good base for users to build high abstraction interfaces.

 

HES-DVM™ supports both SCE-MI macro-based and function-based infrastructures. For function-based interface, HES-DVM provides a SCE-MI 2.0 SystemVerilog transactor compiler capable of translating DPI-C function exports and imports to SCE-MI message ports. After compilation and elaboration, HES-DVM generates synthesizable code with SCE-MI infrastructure that can be implemented on the FPGA hardware. In this process, HES-DVM also creates a DPI-C linkage library that contains all necessary functions that might be used in the high-level testbench.

Determining whether to use macro-based or function-based is purely on the test environment. If utilizing the pre-defined API with macro-based allows enough control over the communication channel – then the function-based interface may not be needed. If writing additional functions to the API are chewing away at verification time – it would be easier to utilize function-based SCE-MI since the user can create their own programming model.  Other important considerations when comparing the two models are shown below:

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For more information on HES-DVM™, including white papers and an illustrated Overview Video, visit www.aldec.com/products/hes-dvm.

 

Bill is responsible for Aldec Hardware Emulation and SoC / ASIC Prototyping. He received his B.S. in Computer Engineering from Auburn University in Alabama in 2011, and currently undertaking his M.S in Electrical Engineering with a focus on hardware emulation methodology and Built-In-Self-Test for high capacity FPGAs. He is also currently a graduate research assistant for the University of Nevada Systems and Integration laboratory studying Network-on-Chip BIST strategies. 

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