Aldec Design and Verification Blog Trending Articles Bridging Simulation and Hardware Advanced Static Linting for FPGA Performance Optimization Scalable Cloud-based CI/CD HDL Verification Environment Navigating VUnit: A Practical Guide to Modifying Testing Approaches Speeding Up Simulation with VUnit for Parallel Testing Introduction to VUnit FPGA Design Verification in a Nutshell All Categories Corporate DO-254 Compliance Embedded Solutions Emulation/Acceleration FPGA Design Functional Verification High Performance Computing Requirements Management SoC and ASIC Prototyping SoC Design and Validation Specialized Applications Linting RISC-V designs with ALINT-PRO As the open-source RISC-V instruction set architecture (ISA) continues to gain momentum, the growing number of RISC-V design solutions, and their flexibility, creates a problem when choosing the most reliable and robust solution from a number of contenders.... Tags:ASIC,FPGA,HDL,Verification,Verilog,Design,Digital,IP,Linting,SoC,SystemVerilog Like(2) Comments (0) Read more Aldec Verification Tools Implement the ASIC Verification Flow Insights from Dr. Stanley Hyduke, Aldec Founder and CEO Aldec has, over the last 30 years, established itself as the preferred provider of high-performance, cost-effective verification tools for use in proving out complex FPGA designs. As the logic capacity and capability... Tags:Aceleration,ASIC,Emulation,Linting,Prototyping,Simulation,Verification Like(2) Comments (0) Read more Much has changed in the last 30 years A New Year’s Reflection from Aldec’s founder and CEO When I first launched Aldec in 1984, home computers hadn’t quite taken off and innovations such as the compact disk and those oversized, power draining cellphones were still struggling to obtain mass acceptance.... Tags:Debugging,Design,Linting,Simulation,UVM,Verification Like(2) Comments (0) Read more
