Time-Saving, Hardware-assisted Verification

For ASIC/SoC Designs

Bill Jason P. Tomas, Product Engineer, Hardware Division
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Identifying effective processes for functional verification of ASIC and SoC designs is of increased significance for engineers due to growing design complexity and integration of embedded components such as CPUs, GPUs, and software device drivers. Overall test time for these systems can include millions, or even billions, of test cycles to completely verify functionality for the average ASIC design. Adding to the challenge, new methodologies must be developed for combined teams of hardware and software engineers to verify both parts of the system function correctly upon integration. These verification concerns are particularly troublesome for companies competing in industries with short time-to-market periods, such as consumer electronics.


Hardware/Software co-verification is the process of verifying that RTL code functions correctly in hardware before the design is committed to fabrication. If bugs are determined to exist in post-silicon production, costly re-spins can ultimately reduce profit margin. Hardware-assisted verification platforms provide users with a solution at all stages of the design cycle with a full range of verification capabilities:

  • Block level: Designers can decrease test time of systems which require many cycles, by offloading the DUT onto hardware while the simulation is controlled by the HDL simulator. This verification method combines benefits of HDL simulation (signal visibility) and prototyping (speed).
  • Transaction level: Emulation at the chip-level can provide up to 10x greater speed that simulation acceleration, allowing up to 100x faster than typical RTL simulation. In this mode the entire DUT and synthesizable portions of the test bench are partitioned and implemented onto the FPGA to obtain MHz emulation speed with debugging capabilities of a simulator. With source level software debugging, static and dynamic probes, users can attain 100% visibility of their design.
  • System-level: Verification with prototyping hardware can assess how a system reacts with various data streams (image, video, etc). Users connect IO interfaces such as HDMI, USB, Wi-Fi, and Bluetooth to the system and observe system level behavior. This environment provides the fastest speed, allowing users to verify functionality in a real-time environment.


Through each of the stages designers require debugging capabilities to provide an oversight of signals while the system is operating. This becomes especially important when debugging large systems, many of which have multiple levels of circuit design.


ASIC/SoC Project Timeline, with and without Hardware/Software co-verification.


In Without co-verification, in Figure 1 the hardware team begins the design process, generating the necessary RTL code, implementing IP cores, and utilizing vendor-specific primitives. Following shortly behind, in parallel, the software team begins generating C/C++ code, operating systems, and software application/drivers. The software teams must then wait for the silicon to be fabricated before testing the software on the hardware board. This pausing of Hardware/Software integration while silicon is fabricated is a clear disadvantage if errors exist when integrating the two portions of the system.



With co-verification, in Figure 2 both hardware and software teams begin integration as soon as stable RTL and software code is available. Both teams can also progress together concurrently, improving performance and resolving issues prior to silicon tape-out, saving cost from silicon re-spins.


The Solution

The HES-7™ ASIC/SoC prototyping board is part of Aldec's Hardware Emulation Solution (HES™) ecosystem which enables users to utilize their prototyping board for hardware-assisted verification without purchasing any additional hardware. HES-DVM™ (Design Verification Manager) enables multiple modes of verification including: acceleration, emulation, prototyping, and virtual modeling to provide users flexibility in verification and debugging at all stages of the design cycle. HES-DVM also integrates ASIC to FPGA conversion tools (clock conversion, memory mapping, partitioning, etc) with many debugging capabilities such as static probes, dynamic probes, memory visibility, black box modules, and mirror-box modules. With design capacity of up to 24 million ASIC gates, HES-7 and HES-DVM are able to handle the demand of large ASIC/SoC designs while meeting the needs of design verification teams. Learn more.


Bill is responsible for Aldec Hardware Emulation and SoC / ASIC Prototyping. He received his B.S. in Computer Engineering from Auburn University in Alabama in 2011, and currently undertaking his M.S in Electrical Engineering with a focus on hardware emulation methodology and Built-In-Self-Test for high capacity FPGAs. He is also currently a graduate research assistant for the University of Nevada Systems and Integration laboratory studying Network-on-Chip BIST strategies. 

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