The Magic of CyberWorkBench

Why you should take a closer look

Guest Blogger: Dr. Benjamin Carrion Schafer, Assistant Professor, Dept. of Electronic and Information Engineering, Hong Kong Polytechnic University
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My first encounter with NEC’s CyberWorkBench (CWB) was in 2003 while attending DAC. Like most people, I was surprised to see a big Japanese company offering EDA tools. NEC is definitely known more for its consumer products and telecommunication equipment. I have to admit, the main reason I stopped at their booth - was that they had hired a magician.

This magician told the audience he would teach us a trick and give us a set of magic cards if we stayed until the end of the presentation. I did and I received my set of magic cards (which I still keep). At the same time I also became a CWB user and even wound up working for NEC.

As an assistant Professor at the Hong Kong Polytechnic University, I currently teach advanced VLSI courses and use CWB. It has some amazing capabilities. Let’s start with the fact that it supports ANSI-C and SystemC. Although SystemC might be a step in the right direction to have a unique standardized IEEE language, supported by all main HLS tools, it is not very intuitive and takes some time to master (especially if the user does not have a C++ background). Here is where ANSI-C support becomes very handy. Most people do know ANSI-C and it is very straightforward to convert any ANSI-C SW description into synthesizable C code.

The second thing that I really like about CyberWorkBench is its intuitive integrated development environment (IDE). Complete multi-process systems can be designed within the IDE which generates numerous reports and offers a QoR visualization tool to fully understand what the synthesizer has done.


State-transition diagrams, schematic viewers (which display the critical paths, which in turn is back-annotated to the original source code),



cross referencing between generated RTL code and C-code, and signal table – just to mention a few.



The fact that CWB runs on Windows and Linux is also extremely helpful. Students with stronger Linux background can benefit from running CWB in batch mode writing their own scripts, while less advanced classes can stick to the IDE.

Another extremely powerful aspect in CWB is it contains hundreds of optimization options which allow you to get the best possible QoR. There are so many options in CyberWorkBench that, whenever I need one and review the documentation, I usually discover the option has already been implemented. CWB even allows manually specifying all these options for advanced users, but also provides automatic ways to synthesize the design. It even includes an automatic design space explorer that creates hardware designs with different area vs. performance trade-offs.



Finally, one of the best features of CWB is its verification environment. It makes no sense to use HLS and write C/SystemC code if the verification has to be done at the RT-level. CWB provides many different model generators ranging from behavioral models to cycle-accurate models to speed up the verification process. It comes with an automatic RTL testbench generator which allows the re-use of the same untimed test data used at the original C-code during the entire verification process all the way down to the RTL simulation. CWB even comes with a hardware source code debugger which allows the debug of the original untimed C code running timed simulations. Pretty cool!

I am excited about the new Aldec-NEC partnership. The HLS technical skills and experience of NEC combined with the depth of Aldec’s technical verification knowledge, international business development and unparalleled support will bring CyberWorkBench to the masses. Then other engineers around the world will benefit from CWB the same way I do.

For more on Aldec and NEC’s new partnership see their recent press release, Aldec and NEC Corp. Ink Distributorship Agreement for CyberWorkBench® ASIC/FPGA High Level Synthesis Solution.


Dr. Benjamin Carrion Schafer received the B.Eng. degree in Electrical and Electronic Engineering from the Polytechnic University of Madrid, Spain, the M.Sc. degree in Microelectronics from Birmingham City University, U.K., and FH-Darmstadt, Germany. After completing his Ph.D. at the University of Birmingham, U.K., he worked in the Computer Science Department at the University of California Los Angeles (UCLA) as a Postdoctoral Researcher from 2003 to 2004. He then joined the School of Electronic Engineering and Computer Science at Seoul National University, Korea, as a Visiting Research Scholar from 2005 to 2007. From 2007 until September 2012, he had been working as a Senior Researcher at System IP Core Department, Central R & D Centre, NEC Corporation, Kawasaki, Japan.

Dr. Carrion Schafer has been engaged in the research and development of VLSI systems, reconfigurable computing, thermal-aware VLSI design and High Level Synthesis (HLS). He served on the TPC of CASES 2006 and as a committee member at the RECONFIG, DAC (user track) and ESLSyn conferences. He is also a member of OSCI's (Accellera) SystemC synthesizable user group committee. He holds an MBA from McGill University.


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