Q3-2012 - Aldec™ Design and Verification Newsletter

Date: 2012/07/18Type: Newsletter

A Simple Approach to Project Task Management

Project Task Management

While developing new code, you likely have often had a quick glimpse of a problem or situation you would like your code to handle but had no time to deal with that idea right away. Perhaps you kept notes on a piece of paper or even filed formal tickets in a bug tracker, but there is a better way - maintaining notes directly in the source code.

Starting with Riviera-PRO release 2012.06, anywhere in a file managed by Riviera-PRO, you can now add a comment which starts with a predefined tag, leaving a note to yourself (or other project team members): Read More

Fast Track to UVM - Training Seminar


Let's be honest - typical, busy hardware designers treat Universal Verification Methodology (UVM) like black magic. Perhaps you’ve learned design subset of SystemVerilog, but have not found the time to play with the advanced verification features required to write with UVM.

For this busy group of SystemVerilog users, Aldec has prepared a new Seminar series, Fast Track to UVM, Read More

Aldec's YouTube Featured Video: Unlock the Powerful Waveform Viewer

Aldec YouTube

Subscribe to AldecInc on YouTube for the latest videos on a variety of design and verification topics along with product demonstration videos.


This month’s featured video Unlock the Powerful Waveform Viewer.

Bartender's Corner: Managing a Cocktail of SPICE, Verilog-AMS, Verilog/SystemVerilog, and VHDL

Creating and verifying mixed-signal (A/MS) integrated circuits is a challenge. Spice-based simulation provides the accuracy needed for the analog design, but is too slow to handle the digital part. Event-driven digital simulation provides the necessary speed to simulate the digital portions, but fails when dealing with the analog parts.

As mixed-signal designs continue to growing in complexity due to functionality and capability requirements, design teams also face pressure to shorten time to market and reduce re-spins. This rapidly changing environment dictates the need for a new A/MS solution Read More

Using Aldec Riviera-PRO to Verify RTL Auto-Generated by Vivado™ HLS

Vivado™ HLS (high-level synthesis) is a new addition to Xilinx tool suite based on extensive evaluation of commercial system-level (ESL) design tools followed by the acquisition of AutoESL Design Technologies, Inc. back in 2010. It enables an alternative approach to the traditional Xilinx FPGA design methodology by enabling algorithmic (rather than typical hardware) development environment. Instead of manually creating a register-transfer-level (RTL) implementation, designers can cut development time by orders of magnitude by representing their algorithms at a higher level of abstraction (C, C++, or SystemC) and verifying reference system behavior at the same level of abstraction. Read More

DO-254 Practitioner's Course: DO-254 Demystified

"The breaking down of the dreaded DO-254 document into manageable sections of information was quite beneficial for me. The instructors were very knowledgeable about the subject and did not hesitate to make the students feel right at home when discussing DO-254."

-Dexter Wimberly, Design Verification Engineer at L3 Communications

"Very good practical experience and helpful hints."

-William Schnepp, Engineering Specialist at Williams International

"The aspects of the course that I found beneficial include the material for FFPA, clarification on level of details that needs to go in the requirements, verification approaches and how the FAA works."

-Santhi Ayyadevar, Verification Lead at eInfochips.

In 3 days, attendees such as airframer and avionics suppliers, Embraer, Honeywell, Parker Aerospace, Turkish Aerospace, Goodrich and SAAB, learned how to apply DO-254 to FPGAs - enabling them to work independently in this area.

For current schedule and locations for Aldec's 3-Day DO-254 Practitioner’s Course, please visit www.aldec.com/do254training.

OS-VVM: Improved Packages and Upcoming Webinar


LIVE WEBINAR: OS-VVM High-Level VHDL Verification - July 19
This webinar will demonstrate the structure and use of OS-VVM packages, paying special attention to Smart Coverage that combines random stimulus and functional coverage to provide faster verification.
Register for webinar, then visit the OS-VVM Forum to submit your questions before the event.

PACKAGE UPDATE: Featuring improvements suggested at the recent OS-VVM User Group Meeting at DAC, revision 2.3.1 of OS-VVM package has recently been posted in the OS-VVM Forum. Highlights include: minor updates to package sources, simplified version of SENSORS example, and improved syntax of the testbench in FIFO example.

ABOUT OS-VVM: Open Source - VHDL Verification Methodology (OS-VVM) delivers advanced verification test methodologies, including Constrained and Coverage-driven Randomization, as well as Functional Coverage, providing advanced features to VHDL design engineers while enabling them to continue to develop using VHDL.Visit www.osvvm.org to learn the latest developments in Open-Source VHDL Verification Methodology.


Product Updates

Riviera-PRO™ 2012.06

Riviera-PRO™ 2012.06 delivers numerous stability and performance improvements, the latest versions of industry-standard verification libraries, new language constructs, new productivity tools in the ever-improving design management and debugging framework, and interfaces to other EDA tools offered via Aldec’s constantly expanding partner network.

Key changes, updates, and new features include:

Core Simulation Engine:
  • Latest verification libraries – UVM 1.1b, VMM 1.1.1a, OS-VVM 2.3.1
  • Simulation performance improvements – SystemVerilog simulation now up to 24% faster!
  • Stability on large designs – over 100 bugs resolved! (see Release Notes)
  • New language constructs in SystemVerilog’2009 and VHDL’2008
Framework and Productivity:
  • Project tasks management (a new Tasks window)
  • Waveform enhanced for displaying of composite objects (arrays, virtual groups)
  • Auto-templates based on current selection, UVM-specific code templates
  • Verilog hierarchical references in Advanced Dataflow
3rd Party Interfaces:
  • Press Release: Agilent SystemVue co-simulation interface (link to RF System simulator)
  • Press Release: Analog/Mixed Signal simulation (SPICE, Verilog-AMS)
  • Verification of custom IPs that target Xilinx Zynq-7000s devices (AXI4 BFM)
  • The latest precompiled simulation libraries for Altera and Xilinx FPGAs
  • Compatibility with the latest release of Xilinx Vivado™ Design Suite

Complete list of new features and enhancements: Riviera-PRO 2012.06 Release Notes

"What's New" presentation: Riviera-PRO 2012.06 What's New

ALINT™ 2012.01

Stay tuned for the next release of ALINT product scheduled to arrive this fall (October’2012). Here is a heads up on some of the new features coming:

  • New rules in ALDEC_VLOG and ALDEC_VHDL basic rule plug-ins, helping to reduce long routing delays. The new rules will be addressing issues associated with fanout, logic levels, and output registers.
  • Tighter integration with Riviera-PRO verification platform. The new version of ALINT is going to be integrated with the project tasks management, a new functionality available with the latest version of Riviera-PRO, 2012.06. Project teams that develop their designs using Aldec tools will be able to take automated code reviews to the next level by quickly creating project tasks based on violations detected during a linting session. For example, a person performing code review or audit would be able to quickly create and delegate action items to the other project team members.
  • Revised exclusions management mechanism for more granular management of project-specific waivers. The updated mechanism will provide means for violation-accurate exclusion management, enabling ALINT users to disable any particular violation based on specific attributes such as location in source and contents of the violation itself.

Active-HDL™ 9.1

Update 4 for Active-HDL 9.1 was recently released, with major features including Library and Design Flow Manager Updates, as well as Bug Fixes. Release of Update 4 also brings support for following vendor tool versions to Design Flow Manager.

  • Actel Designer 10.0
  • Lattice Diamond LSE 1.4
  • Altera QuartusII Synthesis & Implementation 11.1SP2
  • Xilinx ISE/WebPack 14.1


Riviera-PRO™ 2012.06

  • Advanced Verification Platform (OVM/UVM, VMM)
  • IEEE Std. Compliant High-Performance Simulator
  • Assertion-Based Verification (SVA, PSL, OVA)
  • Code and Functional Coverage
  • Powerful IDE and Tcl Scripting
  • Co-Simulation with DSP and RF Tools
  • Linux and Windows 32/64-Bit

Active-HDL™ 9.1

  • FPGA Design & Verification
  • Graphical Design Entry
  • Mixed-Language Simulator
  • Assertions
  • Coverage Tools
  • PCB Interface
  • Documentation Tools

ALINT™ 2012.01

  • Early bugs detection (RTL)
  • Industry-proven design guidelines
  • Guided design refinement (PBL)
  • In-house design expertise automation
  • IDE for in-depth design troubleshooting
  • VHDL, Verilog®, mixed-language
  • C++ based API (custom rules)

HES-DVM™ 2011.10

  • 7MHz Emulation Speed, 37 Million ASIC Gates
  • SCE-MI 2.0 DPI-C Support
  • Integration with Riviera-PRO: Adding/Removing Debugging Signals and Emulation Start/Stop/Step
  • Dynamic Triggers - Flexible Probes

Aldec Quick Tips

Active-HDL's Connect To Simulator feature allows AWC files from other simulations to be connected to running simulation. It automatically traces all relevant signals and links the AWC file to the current simulation database. This feature is available in waveform menu.

Active-HDL allows designers to automatically generate macros/scripts for compilation and simulation. Users can set the the order of compilation from Design Compilation Order option located in Design menu - then go to Design menu and click on Generate Macro.

Riviera-PRO offers a Block | Create Template option (available from the context menu of the HDL Editor) to enable quick creation of custom templates based on a current code selection. The custom template wizard automatically extracts “special fields”, enabling Tab and Shift+Tab hotkey navigation between those fields later, when a template is used. Templates can be shared across organization to facilitate code editing and reuse, see manual for more.

Riviera-PRO's file-level settings enable customizing compilation properties for each individual design file in GUI mode operation (the batch mode users can simply specify multiple compilation commands to achieve the same). The option is available from the right-click menu of Design Manager and comes handy when a design includes files compliant with different standards of the same language, VHDL’2002 and VHDL’2008 for example.

Ask Us a Question

Ask Us a Question

Captcha ImageReload Captcha
Incorrect data entered.
Thank you! Your question has been submitted. Please allow 1-3 business days for someone to respond to your question.
Internal error occurred. Your question was not submitted. Please contact us using Feedback form.