Q2-2012 - Aldec™ Design and Verification Newsletter

Date: 2012/04/12
Type: Newsletter

Free Technical Sessions at DAC

49 DAC

Get the scoop on the newest industry trends! Every year at DAC, Aldec’s top engineers are onsite to deliver informative, one-on-one Technical Sessions to all DAC attendees. Increase your knowledge by registering for a private Technical Session at a time that is convenient for you.

The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. This year’s conference runs June 3-7, 2012 at the Moscone Center in San Francisco, CA.


Click here to Register for an Aldec Technical Session.


UVM in Aldec Tools: Verification and Debugging

Aldec provides the latest support for UVM 1.1a, enabling creation of reusable, robust testbenches and interoperable Verification IPs. In this presentation we will demonstrate Riviera-PRO's support of the latest UVM library along with the graphical debugging features helping designers finding and fixing issues more efficiently. We will present the Read More


10+ MHz Emulation of 100 Million ASIC Gates with True RTL Debugging

Learn how Aldec is able to run emulation at over 10MHz on a 100 Million gate ASIC design. HES (Hardware Emulation System) is an industry proven emulation solution that can be used with off-the-shelf FPGA prototyping boards or custom in-house FPGA boards. Aldec’s emulation software is equipped with automatic partitioning, ASIC to FPGA clock Read More


Using Virtual Platforms with Transaction Level Emulation

Virtual platforms play a significant role in system level development, but require integration with ultra-fast emulation systems for HW/SW co-verification. This presentation will show how HW and SW design teams can now implement virtual models of processors, memory and peripheral modules while the RTL modules run in the emulator board. Read More


High-Level VHDL Verification Doing Well with Help of New OS-VVM Community

You are invited to attend an OS-VVM User Group Meeting (Monday, June 4, 2012 at Aldec’s Booth #2126, Time: tbd) or a schedule a one-on-one Technical Session to learn more about OS-VVM. VHDL is alive and well – used on daily basis by many digital circuit designers and verification engineers. Standard VHDL has all the features necessary to code Read More


Requirements-based FPGA Testing Method for DO-254

DO-254 is currently enforced by the FAA as a means of compliance for the development of airborne electronic hardware containing FPGAs, ASICs and PLDs. DO-254 defines a set of verification objectives and methods that present several new challenges to the avionics community. Learn in this session the most significant challenges that can be Read More


Early Validation of Custom IP for Zynq-based Designs

Learn how Aldec tools, as a part of Xilinx Partnership Ecosystem, address the Hardware Architecture side of Zynq EPP, a new class of product which combines an industry-standard ARM® dual-core Cortex™-A9 MPCore™ processing system with Xilinx 28nm programmable logic. Aldec has been working together with Xilinx to enable the tools for Design Read More


Interoperable IP Encryption (P1735): Safe and Smooth Multi-vendor Encryption Flow

In the modern world of verification, old school proprietary methods of protecting Intellectual Property (IP) are no longer feasible: users want to have freedom to use any tool they want and IP creators have to deal with multiple tool vendors. Fortunately for both, IEEE is in the process of finalizing 1735 standard that enables easy interoperability created Read More


Simulation on the Cloud: Unlimited Possibilities

Aldec has enabled running RTL and Timing simulation on the secured cloud, providing access to a virtually unlimited number of high performance servers. By running on the cloud, customers can cut the regression testing from days to hours or even minutes. Aldec offers flexible cloud usage model, with the time slots from a few to a few hundred hours. Read More


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Click here to Register for an Aldec Technical Session.


Aldec Adds AXI BFM VIP to its Xilinx SecureIP Simulation Library

A vital aspect of any System-on-a-Chip (SoC) is not only the blocks it holds - but also how they are interconnected. With multiple clusters and sophisticated peripherals in today’s SoCs, the interconnect fabric became a major bottleneck, and the traditional interconnection protocol standards were not sufficient to keep up with the constantly growing computing power and match it with adequate bandwidth. To overcome these limitations, Xilinx worked closely with ARM to define the AXI4 (Advanced eXtensible Interface), the fourth generation of AMBA® interface. The AXI specification provides a framework that defines protocols for moving data between IP using a defined signaling standard. Read More

Aldec Launches DO-254 Practitioner's Course

DO-254/ED-80 has been officially enforced by the FAA and other worldwide certification agencies as a means of compliance for all custom micro-coded devices such as FPGAs, PLDs and ASICs. All avionics suppliers and developers must now adhere to the requirements-based design and testing approach imposed by the standard and supply rigorous documentation commensurate to the safety-criticality level of the hardware product. Read More

IEEE Published Paper: FPGA Level In-Hardware Verification for DO-254 Compliance

Aldec’s paper regarding FPGA level in-hardware verification for DO-254 compliance has been published by IEEE and is now available for download. The paper was selected for presentation at the 30th Digital Avionics Systems Conference (DASC) held in Seattle, WA.

The paper, presented by Louie De Luna, DO-254 Program Manager, was well-received by conference attendees and addressed several common issues and limitations caused by the stringent objectives of DO-254 verification Read More

Dynamic Objects in Riviera-PRO Waveform

Riviera-PRO™ enables tracing SystemVerilog classes just like any regular static objects. In the Waveform Window, an object of the class type is presented as a class handle that holds reference to a class instance as its value. Reference is presented using mnemonics that consist of the @ character along with a number (e.g. @2). As class handles can hold references to different instances during simulation progress, actual instance mnemonics are displayed on the waveform and in the Value column, similarly as values of any other data type. Read More

Simulation on the Cloud: Unlimited Possibilities

Free Trial Offer: Aldec is running a free Beta trial program through May 31, 2012 for engineers in North America.

Aldec Cloud Beta

With the release of Aldec Cloud™ (currently in Beta), users may now run a virtually unlimited number of parallel HDL simulation tasks. Customers can leverage Aldec Cloud™ for simulation peak usage, with a significant potential cost savings on hardware infrastructure. With Aldec Cloud™, instead of running regressions for N hours, the customers can utilize N servers and complete the regressions within 1 hour for the same cost.

To read about benefits and best use of Aldec Cloud, as well as watch a recorded video demonstration.

Language neutral libraries for Altera™, Microsemi™ and Xilinx™

Xilinx® first began using SecureIP methodology for IP delivery. These IPs were written using Verilog and SystemVerilog which required Verilog license for simulating them. For the users with a mixed language or Verilog license, this did not create any problems, but VHDL-only license owners were not be able to simulate such IPs as it requires a Verilog simulation license. Since then silicon vendors such as Altera® and Microsemi® also have started providing IPs that have embedded Verilog/SystemVerilog.

Aldec has worked with silicon vendors to provide language neutral libraries that allow users with a VHDL-only license to simulate designs with IP (From Xilinx®, Altera® and Microsemi®) that contains Verilog/SystemVerilog without purchasing a separate Verilog license. These language neutral libraries are watermarked for VHDL-only customers and can be downloaded from Aldec website.

Open Source VHDL Verification Methodology (OS-VVM) Update

OS-VVMApril marks the launch of a new website dedicated to Open Source VHDL Verification Methodology. OS-VMM delivers advanced verification test methodologies, including Constrained and Coverage-driven Randomization, as well as Functional Coverage, providing advanced features to VHDL design engineers while enabling them to continue to develop using VHDL.

Aldec, in its continued commitment to provide continued support to the VHDL design community, has helped establish the OS-VMM Forum, where users are encouraged to work together to help grow the methodology. We invite you get involved by visiting the new site’s blog, commenting on articles, and posting your questions and suggestions in the forums. Visit www.osvvm.org for more information, to download the documentation and software package, as well as to participate in future development.


Product Updates

ALINT™ 2012.01

The latest release of ALINT delivered valuable tools for efficient project collaboration and information sharing across your organization. These new tools include:

  • Interactive HTML Reportingthat enables efficient design analysis even without the tool installed. This new report delivers a unique experience of interactive violation report analysis in a comfort of your favorite web browser. Enabling almost all the features of the dedicated Violation Viewer, including the cross-probing, it is absolutely portable and independent from the design and its sources.
  • Exclusion Files Annotation, the essential tool for project documentation that enables justifying every waiver introduced. Every single exclusion can be justified now and the appropriate comments appear in the Violation Viewer (applies when "irrelevant" coding standard violations are not filtered out).
  • Windows 64-bit linting. With a dedicated build for 64-bit Windows® platform available, the tool is free of memory limitations previously imposed by the 32-bit computing environment and is capable of analyzing truly large and memory hungry designs.

In addition, we have implemented numerous productivity features based on requests coming from our customers - make sure to leverage all these benefits as soon as the new build is available!

Riviera-PRO™ 2012.02

The latest release of Riviera-PRO™ brought enhanced support for verification environments that are constructed with the Universal Verification Methodology (UVM) class library, new SystemVerilog IEEE 1800™-2009 and VHDL IEEE 1076™-2008 constructs, and numerous new features in the Waveform and built-in HDL Editor that make it easier to debug complex SoC designs.

  • UVM-aware Framework. Starting with 2012.02 product release, Riviera-PRO features multi-threaded SystemVerilog compilation (at least 25% speedup in compilation of a typical UVM-based testbench), location-accurate messaging (source pointers are now based on the new $aldec system functions behind the standard UVM message reporting interfaces), reduced level of compiler “noise” to ensure clean and concise logs, and new environment variables that facilitate the use of the UVM library itself and make scripting much easier.
  • Language Support. 2012.02 product release enables quite a few new SystemVerilog, SystemVerilog Assertions (SVA), and VHDL constructs. Preliminary support for global constraints, forward typedef, extern module declarations, dynamic arrays in constraint blocks – just to mention some of the most useful SystemVerilog constructs here, with all the added benefits explained in the Release Notes and What’s New presentation (www.aldec.com/products/riviera-pro). On the SVA side, Riviera-PRO introduces full support for the multi-clocked properties and sequences – great news for verification engineers who are dealing with multiple clock domain designs. On the VHDL side, Aldec became closer than ever to the full support for 1076™-2008, by adding the 'force' and 'release' signal assignment statements.
  • Debugging and Productivity. Starting with 2012.02 it is now possible to log class objects and display them in the Waveform Viewer. The tool is also equipped with the new ability of logging the Information, Warning, and Error messages generated during simulation runtime. For every message logged, the appropriate marker is displayed in the Waveform, providing a link for further analysis in a dedicated Message Viewer as necessary. Keep pass with the new features available in the Waveform Viewer, automatic “background compilation” has been added to the HDL Editor to help nail down syntax mistakes on-the-fly.

Active-HDL™ 9.1

Update 2 for Active-HDL 9.1 was recently released, with major features including Library and Design Flow Manager Updates, as well as Bug Fixes. Release of Update 2 also brings support for following vendor tool versions to Design Flow Manager.

  • Actel Designer 10.0
  • Lattice Diamond LSE 1.4
  • Altera QuartusII Synthesis & Implementation 11.1SP2
  • Xilinx ISE/WebPack 13.4

Active-HDL™ Student Edition

Recently released Active-HDL Student Edition is packed with many new features and enhancements to provide students a robust tool with support for latest language standard and FPGA devices. Major highlights for this release include:

  • Support for VHDL 2008 and SystemVerilog 2009 (Design Constructs)
  • Support for latest FPGA devices in Design Flow Manager
  • Code2Graphics tool to convert HDL source code into block and state diagrams
  • Documentation tool to export projects to HTML and PDF


Riviera-PRO™ 2012.02

  • Advanced Verification Platform (OVM/UVM, VMM)
  • High-Performance Simulator
  • Assertion-Based Verification
  • Code and Functional Coverage
  • Transaction-Level Debugging
  • DSP Co-Simulation with MATLAB®

Active-HDL™ 9.1

  • FPGA Design & Verification
  • Mixed-Language Simulator
  • Assertions
  • Coverage Tools
  • PCB Interface
  • Documentation Tools

ALINT™ 2012.01

  • Early Bugs Detection
  • Phase-Based Linting Methodology
  • Over 400 Design Rules
  • VHDL, Verilog®, & Mixed
  • User-defined Rules
  • Integrated Debugging Environment

HES-DVM™ 2011.10

  • 7MHz Emulation Speed, 37 Million ASIC Gates
  • SCE-MI 2.0 DPI-C Support
  • Integration with Riviera-PRO: Adding/Removing Debugging Signals and Emulation Start/Stop/Step
  • Dynamic Triggers - Flexible Probes

Aldec Quick Tips

In the default mode, Riviera-PRO does not record messages during simulation runtime. To enable the message recording and see the Info, Warning, and Error markers in the Waveform Viewer, use -logmsg argument for asim command or logmsg command: logmsg {all | assert | error | info | note | warning}.

Instant analysis is automatically performed while editing source code. If the new code contains errors, watch out for an error marker on the margin of HDL Editor. Note: Hovering a mouse cursor over an error marker displays a tooltip.

The Advanced Clipboard is available by Ctrl+Shift+V. Riviera-PRO’s HDL Editor stores the last 10 items copied to the clipboard, and allows selecting an item to paste from the enumerated object list.

Access new training material for Active-HDL and Riviera-PRO. These training docs are posted under the download section of Aldec’s website. You will need to Sign In to access this material.

Active-HDL provides a utility that allows importing simulation scripts coming from the Altera Qsys system integration tool.

Keep it small! When working with mixed-language designs in your tools it is good idea to keep all names (ports, parameters, modules/components) that cross language borders in lowercase and without fancy characters. If you use capital letters in those names, tools may be forced to turn them into extended identifiers to maintain consistent data flow.

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