Simulating AXI-Based Systems Created Using Xilinx Platform Studio

EDK (Embedded Development Kit) is a suite of tools and IP that enables you to design a complete embedded processor system for implementation in a Xilinx FPGA device. Xilinx Platform Studio (XPS) is a part of EDK, the development environment used for designing the hardware portion of your embedded processor system. The functionality of your hardware portion can be verified by running the design through an HDL simulator, e.g. you may use Aldec Active-HDL or Riviera-PRO to simulate embedded designs (Figure 1).

Figure 1. Embedded Design Flow with XPS and Riviera-PRO

The verification process structure, including HDL files for simulation, is set up automatically by XPS. For XPS-based systems, pcore wrappers around the AXI BFMs are provided under Verification in the EDK Install IP catalog (1) . The AXI BFMs can be added and connected to an EDK system in the same way as any other AXI-based IP core: add the core to the project, parameterize the core, and connect the core to the system (by connecting the "Bus Interface" of the related AXI interface).

Figure 2. CIP Wizard in XPS

To create a custom AXI-based based IP with AXI BFM simulation, you may use the XPS Create IP (CIP) Wizard (Figure 2) available in the XPS GUI. For example:

  1. Select Hardware—Create or Import Peripheral to enable the wizard

  2. Click Next and select Create templates for a new peripheral

  3. Click Next and select the repository for the peripheral

  4. Click Next and name the IP (custom_axi_ip)

  5. Click Next and select the bus interface (AXI4: Bust Capable…)

  6. Click Next and check User logic master support

  7. Click Next until the Peripheral Simulation Support page is reached

  8. Check Generate BFM simulation platform (Figure 3), click Next, Next, and Finish

Figure 3. Generating AXI BFM Simulation Platform in XPS

The Wizard matches your custom IP core with an appropriate AXI BFM project and generates a directory with the IP and AXI BFM wrapper files to be used with simulations (Figure 4).

Figure 4. CIP Wizard Output Directory

The AXI BFM simulation can be executed from /devl/bfsim subdirectory (Xilinx provides AXI BFM wrapper files to be used with AXI-based IP BFM simulations). When an AXI-based master/slave IP is generated, a corresponding AXI BFM core is added to assist in developing the custom core.

In the current example, “User Logic Master Support” is enabled. Therefore, custom_axi_ip has an AXI4 Master interface and an AXI4-Lite Slave interface, which is connected through an AXI4 bus and AXI4-Lite bus interface, respectively. In the AXI BFM simulation directory, the AXI4_MASTER_BFM_WRAPPER, AXI4_LITE_MASTER_BFM_WRAPPER and AXI4_SLAVE_BFM_WRAPPER are used for simulation. To simulate the generated AXI-based IP within Riviera-PRO, you need to take the following steps:

Step 1 Use the simgen command (<XILINX_ISE_INSTALL_DIR>/ISE_DES/EDK/bin/<OS>/) to generate HDL simulation files. The key arguments are explained in the following listing:

simgen <path_to_XPS_project_file>   // bfm_system.mhs
-p     <part>                       // xc6vlx240tff1156-1
-lang  <language>                   // Verilog
-lp    <simulation_libraries_path>  // /home/Xilinx/
-s     mgm                          // Target Simulator (mgm = Mentor Graphics ModelSim®)
-tb                                 // Generate Testbench template
-od    <output_directory>           // /devl/bfmsim

Wait until generation process completes (“Simulation Model Generator done!” message).

Step 2 Copy the bfm_system_tb.v testbench file from /devl/bfmsim/scripts to the newly generated /devl/bfmsim/simulation/behavioral folder.

Figure 5. Riviera-PRO Batch Replacement Dialog

Step 3 Convert the .do macro at /devl/bfmsim/simulation/behavioral folder to Riviera-PRO format:

  1. Replace the -novopt with -dbg in all .do files.

    Note: you may use Riviera-PRO’s Edit—Replace in Files tool (Figure 5) for batch replacement.

  2. Rename to in the

  3. Replace "/bfm_system_tb${ps}dut" with "sim:/bfm_system_tb${ps}dut" in * files.

  4. Replace the -noupdate with “” (i.e. remove it) in all the * files.

  5. Comment out the “Wave window configuration information” section in

Step 4 Prepare the macro and save it in the /devl/bfmsim/simulation/behavioral folder:

do  # Define macros and commands
c                       # Compile BFM test modules
s                       # Load BFM test platform
w                       # Load Waveform Viewer
run 100 us              # Run test time

Step 5 Launch Riviera-PRO and type do in the Console. Assuming, the AXI BFM license is available (refer to Simulating AXI-based Designs in Active-HDL or Simulating AXI-based Designs in Riviera-PRO for details on how to set up your environment), the simulation will start running with the appropriate activities indicated in Waveform Viewer. Note that AXI BFM configuration details can be observed in Riviera-PRO Console:

# KERNEL: BFM Xilinx: License succeeded for Xilinx_AXI_BFM, version 2014.100000
# KERNEL: **********************************************************
# KERNEL: * Cadence AXI 4 LITE MASTER BFM                          *
# KERNEL: **********************************************************
# KERNEL: **********************************************************

The sample Riviera-PRO waveform (Figure 6) illustrates the following transactions performed through the AXI4 bus by the BFM_BURST_PROCESSOR:

  1. Write burst to BFM_MEMORY at address 0x4000000

  2. Write burst to BFM_MEMORY at address 0x4000040

  3. Read burst from BFM_MEMORY at address 0x4000040

Figure 6. BFM_BURST_PROCESSOR Simulation Waveform Fragment


  1. AXI Bus Functional Models v2.1 Product Specification

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