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Q1-2011 - Aldec™ Design and Verification Newsletter

Date: 2011/01/13Type: Newsletter

2010: Looking Back and Moving Forward

During 2010 Aldec achieved double digit growth for the second consecutive year and has opened offices in Taiwan and Israel to support its global expansion plans. In Japan, Aldec doubled the size of its operations and added the necessary customer support resources to support its growth in India and China.

Aldec has three business units to support its verification deployment strategies - Software Verification (VHDL, Verilog and SystemVerilog) Hardware Assisted Verification and Specialty Solutions to support DO-254 and RTAX prototyping adapters - all business units have shown growth and have a good pipeline moving into the next year.

In late 2010, Aldec successfully deployed SystemVerilog Verification into several large multinationals and expects to see this trend continue. In addition, Aldec has signed an OEM agreement with Altium™ Limited (ASX:ALU) to add Aldec's FPGA simulation capabilities to Altium Designer and also extended its existing OEM agreement with Lattice™ Semiconductor (NASDAQ:LSCC) for the continue distribution of Aldec's FPGA simulator to Lattice ispLever and Diamond customers.
View All 2010 Press Releases

Technology


Cryptology - The Gateway to IP Encryption
Cryptology (the study of encrypting and decrypting information) has multiple practical applications in telecommunication, media, on-line banking and commerce, HDL Intellectual Property delivery, etc. Generally available references on this subject are either too brief (explaining terms, but not applications) or too detailed (overflowing beginners with irrelevant information). Aldec solves this problem with an hour-long webinar presenting the information about cryptology needed to understand its typical technical applications. The webinar is simple, yet highly informative; it uses diagrams and animations excessively and avoids advanced math whenever it is not absolutely required. The knowledge acquired during this webinar will be helpful while working on any encryption-related project or attending next webinar dealing with interoperable system of IP encryption.

Register for Webinar

 

Hardware-Assisted Simulation with Quick Error Detection
As designs get more complex and chip density increase, functional verification becomes more and more overwhelming and time-consuming. To help verification engineers reduce their verification tasks and decrease the number of builds (Synthesis and P&R) necessary for debugging, Aldec recently added an advanced debugging feature in HES called Mirror-Box. Mirror-Box allows any module of the accelerated design to be mirrored such that two implementations of the same module are generated. One implementation can be used to be simulated in the FPGA hardware, and the other implementation can be used to be simulated in the HDL simulator. In doing this, the verification engineer can make changes to the RTL module selected as Mirror-Box while the rest of the design runs in the FPGA hardware. For quick detection of differences or errors between FPGA hardware and HDL simulation, the user can switch between the two mirrored modules easily without having to rerun Synthesis and P&R. This eliminates the long and daunting task of rebuilding the FPGA several times during debugging which ultimately helps in detecting more errors and bugs per day.
Download White Paper: Simulation Acceleration in HES

 

Active-HDL 8.3 sp1 Code Coverage Tool Assessment and Qualification
Aldec has done its due diligence to address the safety-critical requirements imposed by DO-254 certification authorities regarding Code Coverage. Code Coverage analysis can be used to identify sections of source code which have not been executed by the testbench, and determine the sections that are executed more frequently than others. Since Code Coverage analysis is essential to the verification process of safety-critical designs, ensuring that it provides accurate coverage counts and results is absolutely vital. Aldec created a package of VHDL test cases and documentation (Tool Operational Requirements, Tool Test Plan, Tool Qualification Accomplishment Summary, Test Analysis Documentation) proving that Active-HDL's Line, Branch and Statement Coverage show accurate coverage counts as expected. Applicants may use the full documentation package provided by Aldec for their certification application avoiding a very tedious task should they choose to do it on their own.

Product updates

Riviera-PRO™ 2010.10
Released in November 2010, Riviera-PRO 2010.10 supports the latest version of Universal Verification Methodology (UVM) and provides powerful debugging tools for system-level verification environments. The next release is expected in the end of February 2011 and enhances the UVM tool set with intriguing new features such as displaying of transactions in the Waveform. Another hot deliverable for Riviera-PRO 2011.02 is Beta support of 64-bit Windows.

Active-HDL™ 8.3
Active-HDL was awarded the 2010 Best FPGA Development Tool by the Ministry of Industry and Information Technology of the People's Republic of China. The award recognized Active-HDL as the superior choice for FPGA designers in China based on its powerful, easy-to-use FPGA design creation, project management and mixed VHDL and Verilog verification and excellent documentation toolset.

ALINT™ 2010.10
ALINT 2010.10 was released in December 2010 and delivers Phase-Based Linting (PBL), a new methodology which significantly improves user productivity and overall efficiency of the entire linting process. PBL puts clear priorities into the design analysis process by reducing the total number of issues to deal with and minimizing the number of design refinement iterations. Look for ALINT 2010.10 Service Release 1, anticipated in March 2011, to include numerous customer-requested features and enhancements.

Products

Riviera-PRO™ 2011.02

  • Advanced Verification Platform
    (OVM/UVM, VMM)
  • High-Performance Simulator
  • Assertion-Based Verification
  • Code and Functional Coverage
  • Transaction-Level Debugging
  • DSP Co-Simulation with
    MATLAB®
  • Now with 64-bit Windows® & Linux Simulation

Active-HDL™ 8.3 sp 1

  • FPGA Design & Verification
  • Mixed-Language Simulator
  • Assertions
  • Coverage Tools
  • PCB Interface
  • Documentation Tools

ALINT™ 2010.10

  • Early Bugs Detection
  • Phase-Based Linting Methodology
  • Over 400 Design Rules
  • VHDL, Verilog®, & Mixed
  • User-defined Rules
  • Integrated Debugging Environment

HES-DVM™ 2011.10

  • 4MHz Emulation Speed,
    37 Million ASIC Gates
  • SystemVerilog
  • 100% Visibility for Dynamic
    Debugging
  • Guided Partitioning
    Visualization
  • Integration with Riviera-PRO Post Simulation Debug
  • 6 Virtex-6™ Board Support (DINI Group DN2076K10™) 

Tech Fact
Assessment and Qualification are often mistaken to have the same meaning and purpose in DO-254. However, they are two completely different paths according to chapter 11.4 Tool Assessment and Qualification Process. Assessment or Independent Assessment is the means of verifying the correctness of the tool output by using an independent tool. Qualification or Basic Tool Qualification is the means of establishing and executing a concise plan to confirm that the tool produces correct outputs for its intended purposes. The latter normally involves more documentation, thus, more time-consuming.


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